Stratix 10 Configuration Features; Device Security; Configuration Via Protocol - Intel Stratix 10 Configuration User Manual

UG-S10CONFIG | 2018.11.02
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4. Stratix 10 Configuration Features

4.1. Device Security

Note: Contact your Intel sales representative for more information about the device security
support in Intel Stratix 10 devices.
The Intel Stratix 10 device provides the following flexible and robust security features
to protect sensitive data and intellectual property:
• User image authentication and encryption
• Public-Key based authentication
• Advanced Encryption Standard (AES)-256 Encryption
• JTAG Disable
• JTAG Debug Disable/Enable
• Side channel protection
• Physical anti-tampering

4.2. Configuration via Protocol

The CvP configuration scheme creates separate images for the periphery and core
logic. You can store the periphery image in a local configuration device and the core
image in host memory, reducing system costs and increasing the security for the
proprietary core image. CvP configures the FPGA fabric through the PCI Express*
(PCIe) link and is available for Endpoint variants only.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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