Understanding Seus; Reading The Unique 64-Bit Chip Id; Understanding And Troubleshooting Configuration Pin Behavior - Intel Agilex Configuration User Manual

6.5. Understanding SEUs

SEUs are rare, unintended changes in the state of an FPGA's internal memory elements caused by cosmic radiation effects.
The change in state is a soft error and the FPGA incurs no permanent damage. Because of the unintended memory state, the
FPGA may operate erroneously until background scrubbing fixes the upset.
The Intel Quartus Prime software offers several features to detect and correct the effects of SEU, or soft errors, as well as to
characterize the effects of SEU on your designs. Additionally, some Intel FPGAs contain dedicated circuitry to help detect and
correct errors.
For more information about SEUs, refer to Intel Agilex SEU Mitigation User Guide.

6.6. Reading the Unique 64-Bit CHIP ID

The Chip ID Intel IP core in each Intel Agilex device stores a unique 64-bit chip ID. After the Chip ID Intel IP core receives a
valid clock input, the chip ID is available on the
interface. The chip ID may be useful for debugging. For more information about the chip ID refer to the Chip ID Intel FPGA IP
Cores User Guide .
Related Information
Chip ID Intel FPGA IP Cores User Guide

6.7. Understanding and Troubleshooting Configuration Pin Behavior

Configuration typically fails for one of the following reasons:
• The host times outs
• A configuration data error occurs
• An external event interrupts configuration
• An internal error occurs
Intel ® Agilex ™ Configuration User Guide
104
output port. You can read the chip ID using the JTAG
chip_id[63:0]
6. Intel Agilex Debugging Guide
UG-20205 | 2019.04.03
Send Feedback