Functional Operation; Figure 11. Duty Cycle Of 20; Figure 12. Duty Cycle Of 50; Figure 13. Duty Cycle Of 80 - Intel Quark SE Series Platform Manual

Pulse Width Modulation (PWM)

Figure 11. Duty Cycle of 20%

Figure 12. Duty Cycle of 50%

Figure 13. Duty Cycle of 80%

5.2

Functional Operation

Each counter is identical, has an associated PWM Output, and can be individually
configured with the following options:
 Enable
 PWM Mode or Timer Mode

PWM Duty Cycle and Frequency
 Timer Timeout Period
 Interrupt Masking
In PWM Mode, the high and low times can be configured as follows. This assumes a
nominal system clock frequency of 32 MHz. The values, in nanoseconds, will differ
if the system clock frequency is changed.

Table 10. PWM Timing

Low Time Granularity
Low Time Range
High Time Granularity
High Time Range
PWM Mode supports the following maskable interrupt source:
 Both edges of the PWM Output signal
In Timer Mode, the timeout period can be configured as follows. This assumes a
nominal system clock frequency of 32 MHz. The values, in nanoseconds, will differ
if the system clock frequency is changed.
June 2017
Document Number: 334715-004EN
Characteristic Value (System Clock Cycles)
1
2 to 4294967296 (2^32)
1
2 to 4294967296 (2^32)
Intel® Quark™ SE Microcontroller C1000
Value (Time)
31.25 ns
62.5 ns to 134.22 s
31.25 ns
62.5 ns to 134.22 s
Platform Design Guide
29