Differential I/O Bit Position - Intel Agilex User Manual

5. Intel Agilex High-Speed SERDES I/O Architecture
UG-20214 | 2019.04.02
Signal
fast_clock
load_enable
tx_out

5.2.4. Differential I/O Bit Position

Data synchronization is necessary for successful data transmission at high
frequencies.
Figure 27. Bit-Order and Word Boundary for One Differential Channel
This figure shows the data bit orientation for a channel operation and is based on the following conditions:
• The serialization factor is equal to the clock multiplication factor.
• The phase alignment uses edge alignment.
• The operation is implemented in hard SERDES.
Transmitter Channel Operation (x8 Mode)
tx_coreclock
tx_out
Table 15. Differential Bit Naming
This table lists the conventions for differential bit naming for 12 differential channels. The MSB and LSB
positions increase with the number of channels used in a system.
Receiver Channel Data Number
1
2
3
4
5
6
7
8
9
10
11
12
Send Feedback
(Supported serialization factors: 3–10)
Clock for the transmitter
Enable signal for serialization
LVDS output data stream
Previous Cycle Current Cycle
7 6 5
X X X X X X X X
MSB
Note: These waveforms are only functional waveforms and do not convey timing information
MSB Position
Description
Next Cycle
4 3 2 1 0
X X X X X X
LSB
Internal 8-Bit Parallel Data
7
15
23
31
39
47
55
63
71
79
87
95
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
X X
LSB Position
0
8
16
24
32
40
48
56
64
72
80
88
41