Media-Independent Interface: Mii; Table 140. Clock Range; Figure 316. Mdio Timing And Frame Structure - Read Cycle; Figure 317. Media Independent Interface Signals - ST STM32F207 Series Reference Manual

RM0033
MDC
MDIO
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock
whose source is the application clock (AHB clock). The divide factor depends on the clock
range setting in the MII Address register.
Table 140
100, 101, 110, 111
28.4.2

Media-independent interface: MII

The media-independent interface (MII) defines the interconnection between the MAC
sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.
Ethernet (ETH): media access control (MAC) with DMA controller

Figure 316. MDIO timing and frame structure - Read cycle

32 1's 0 1 1 0
A4 A3 A2 A1 A0 R4 R3
Start
OP
Preamble
of
code
frame
Data to PHY
shows how to set the clock ranges.
Selection
000
001
010
011

Figure 317. Media independent interface signals

STM32 MCU
R2 R1 R0
Register address Turn
PHY address

Table 140. Clock range

HCLK clock
60-100 MHz
100-120 MHz
20-35 MHz
35-60 MHz
Reserved
TX _CLK
TXD[3:0]
TX_EN
RX_CLK
RXD[3:0]
RX_ER
RX_DV
CRS
COL
MDC
MDIO
RM0033 Rev 9
D15 D14 D1 D0
data
around
Data from PHY
MDC clock
AHB clock / 42
AHB clock / 62
AHB clock / 16
AHB clock / 26
-
External
PHY
ai15627
ai15622c
845/1381
956