Rtc Time Stamp Time Register (Rtc_Tstr); Rtc Time Stamp Date Register (Rtc_Tsdr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus
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RM0402
22.6.13

RTC time stamp time register (RTC_TSTR)

Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
MNT[2:0]
r
r
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 PM: AM/PM notation
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.
Note:
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
22.6.14

RTC time stamp date register (RTC_TSDR)

Address offset: 0x34
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
WDU[1:0]
r
r
r
28
27
26
25
Res.
Res.
Res.
12
11
10
9
MNU[3:0]
r
r
r
r
0: AM or 24-hour format
1: PM
28
27
26
25
Res.
Res.
Res.
12
11
10
9
MT
MU[3:0]
r
r
r
r
24
23
22
Res.
Res.
PM
r
8
7
6
Res.
ST[2:0]
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
r
RM0402 Rev 6
Real-time clock (RTC)
21
20
19
18
HT[1:0]
HU[3:0]
r
r
r
r
5
4
3
2
SU[3:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
DT[1:0]
r
r
r
r
17
16
r
r
1
0
r
r
17
16
Res.
Res.
1
0
DU[3:0]
r
r
647/1163
655

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