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Bits
Name
60
FUNFE Embedded floating-point underflow exception enable.
0 Exception disabled.
1 Exception enabled. A floating-point data exception is taken if FUNF or FUNFH is set by a floating-point
instruction.
61
FOVFE Embedded floating-point overflow exception enable.
0 Exception disabled.
1 Exception enabled. If the exception is enabled, a floating-point data exception is taken if FOVF or FOVFH
is set by a floating-point instruction.
62–63 FRMC Embedded floating-point rounding mode control.
00 Round to nearest.
01 Round toward zero.
10 Round toward +infinity.
11 Round toward -infinity.
2.7.2
Accumulator (ACC)
The 64-bit architectural accumulator register holds the results of the multiply accumulate (MAC) forms of
SPE integer instructions. The accumulator allows back-to-back execution of dependent MAC instructions,
as in the inner loops of DSP code such as finite impulse response (FIR) filters. The accumulator is partially
visible to the programmer in that its results do not have to be explicitly read to use them. Instead, they are
always copied into a 64-bit destination GPR specified as part of the instruction. However, the accumulator
must be explicitly initialized when a new MAC loop starts. Based upon the type of instruction, an
accumulator can hold either a single 64-bit value or a vector of two 32-bit elements.
The Initialize Accumulator instruction (evmra) initializes the accumulator. This instruction is described
in the EREF.
2.8
Interrupt Registers
This section describes the registers for interrupt handling.
2.8.1
Interrupt Registers Defined by Book E
This section describes the following registers and their fields:
•
Section 2.8.1.1, "Save/Restore Register 0 (SRR0)"
•
Section 2.8.1.2, "Save/Restore Register 1 (SRR1)"
•
Section 2.8.1.3, "Critical Save/Restore Register 0 (CSRR0)"
•
Section 2.8.1.4, "Critical Save/Restore Register 1 (CSRR1)"
•
Section 2.8.1.5, "Data Exception Address Register (DEAR)"
•
Section 2.8.1.6, "Interrupt Vector Prefix Register (IVPR)"
•
Section 2.8.1.7, "Interrupt Vector Offset Registers (IVORs)"
•
Section 2.9, "Exception Syndrome Register (ESR)"
Freescale Semiconductor
Table 2-9. SPEFSCR Field Descriptions (continued)
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Register Model
2-19
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