CHAPTER 15 I
A sample flow is given below.
7. Example of occurrence of an interrupt (INT bit=1) upon detection of "AL bit=1"
When an instruction which generates a start condition is executed (setting the MSS bit to "1") with
"bus busy" detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detection
of "AL bit=1".
Figure 15.2-3 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs
Master mode setting
Set the MSS bit in the bus control register (IBCR) to "1".
Wait* for the time for three-bit data transmission at the I
transfer frequency set in the clock control register (ICCR).
BB bit=0 and AL bit=1?
Set the EN bit to "0" to initialize I
to normal process
Interrupt in the ninth clock cycle
Clearing the AL bit by software
Releasing the SCL by clearing
the INT bit by software