Control Register 3 (Usart_Cr3) - ST STM32F410 Reference Manual

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
Bit 8 LBCL: Last bit clock pulse
This bit allows the user to select whether the clock pulse associated with the last data bit
transmitted (MSB) has to be output on the SCLK pin in synchronous mode.
0: The clock pulse of the last data bit is not output to the SCLK pin
1: The clock pulse of the last data bit is output to the SCLK pin
Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected
by the M bit in the USART_CR1 register.
2: This bit is not available for UART4 & UART5.
Bit 7 Reserved, must be kept at reset value
Bit 6 LBDIE: LIN break detection interrupt enable
Break interrupt mask (break detection using break delimiter).
0: Interrupt is inhibited
1: An interrupt is generated whenever LBD=1 in the USART_SR register
Bit 5 LBDL: lin break detection length
This bit is for selection between 11 bit or 10 bit break detection.
0: 10-bit break detection
1: 11-bit break detection
Bit 4 Reserved, must be kept at reset value
Bits 3:0 ADD[3:0]: Address of the USART node
This bit-field gives the address of the USART node.
This is used in multiprocessor communication during mute mode, for wake up with address mark
detection.
Note: These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.
24.6.6

Control register 3 (USART_CR3)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value
Bit 11 ONEBIT: One sample bit method enable
Bit 10 CTSIE: CTS interrupt enable
Note: This bit is not available for UART4 & UART5.
676/771
27 26 25
Res. Res. Res.
11 10 9
ONEBIT CTSIE CTSE
rw rw rw
This bit allows the user to select the sample method. When the one sample bit method is
selected the noise detection flag (NF) is disabled.
0: Three sample bit method
1: One sample bit method
0: Interrupt is inhibited
1: An interrupt is generated whenever CTS=1 in the USART_SR register
24 23 22
Res. Res. Res.
8 7 6
RTSE DMAT DMAR SCEN
rw rw rw
RM0401 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
NACK HDSEL IRLP
rw rw rw rw
17 16
Res. Res.
1 0
IREN EIE
rw rw