Can Mailbox Registers; Figure 312. Rx And Tx Mailboxes - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus

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Bits 19:16 TS1[3:0]

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:0 BRP[9:0]

CAN mailbox registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to

Section 27.7.5: Message storage

Transmit and receive mailboxes have the same registers except:

The FMI field in the CAN_RDTxR register.

A receive mailbox is always write protected.

A transmit mailbox is write-enabled only while empty, corresponding TME bit in the

CAN_TSR register set.

There are three TX Mailboxes and two RX Mailboxes , as shown in

Mailbox allows access to a 3-level depth FIFO, the access being offered only to the oldest

received message in the FIFO. Each mailbox consist of four registers.

Time segment 1

These bits define the number of time quanta in Time Segment 1

x (TS1[3:0] + 1)

For more information on bit timing refer to

Baud rate prescaler

These bits define the length of a time quanta.

= (BRP[9:0]+1) x t

for detailed register mapping.

Three Tx Mailboxes

RM0033 Rev 9

Controller area network (bxCAN)

312. Each RX

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