Can Mailbox Registers; Figure 333. Can Mailbox Registers - ST STM32F412 Reference Manual

Controller area network (bxCAN)
Bits 25:24 SJW[1:0]
These bits define the maximum number of time quanta the CAN hardware is allowed to
lengthen or shorten a bit to perform the resynchronization.
t
Bit 23 Reserved, must be kept at reset value.
Bits 22:20 TS2[2:0]
These bits define the number of time quanta in Time Segment 2.
t
Bits 19:16 TS1[3:0]
These bits define the number of time quanta in Time Segment 1
t
For more information on bit timing, refer to
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 BRP[9:0]
These bits define the length of a time quanta.
t
28.9.3

CAN mailbox registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to
Section 28.7.5: Message storage on page 936
Transmit and receive mailboxes have the same registers except:
•
The FMI field in the CAN_RDTxR register.
•
A receive mailbox is always write protected.
•
A transmit mailbox is write-enabled only while empty, corresponding TME bit in the
CAN_TSR register set.
There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level
depth FIFO, the access being offered only to the oldest received message in the FIFO.
Each mailbox consist of 4 registers.
CAN_RI0R
CAN_RDT0R
CAN_RL0R
CAN_RH0R
FIFO0
CAN TX mailbox identifier register (CAN_TIxR) (x = 0..2)
Address offsets: 0x180, 0x190, 0x1A0
Reset value: 0xXXXX XXXX (except bit 0, TXRQ = 0)
All TX registers are write protected when the mailbox is pending transmission (TMEx reset).
952/1163
:
Resynchronization jump width
= t x (SJW[1:0] + 1)
RJW q
:
Time segment 2
= t x (TS2[2:0] + 1)
BS2 q
:
Time segment 1
= t x (TS1[3:0] + 1)
BS1 q
:
Baud rate prescaler
= (BRP[9:0]+1) x t
q PCLK

Figure 333. CAN mailbox registers

CAN_RI1R
CAN_RDT1R
CAN_RL1R
CAN_RH1R
FIFO1
Section 28.7.7: Bit timing on page
for detailed register mapping.
CAN_TI0R
CAN_TDT0R
CAN_TDL0R
CAN_TDH0R
Three Tx Mailboxes
RM0402 Rev 6
938.
CAN_TI1R CAN_TI2R
CAN_TDT1R CAN_TDT2R
CAN_TDL1R CAN_TDL2R
CAN_TDH1R
CAN_TDH2R
RM0402
MS31003V2