Dac Software Trigger Register (Dac_Swtrigr); Dac Channel1 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12R1) - ST STM32F205 series Reference Manual

RM0033
11.5.2

DAC software trigger register (DAC_SWTRIGR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SWTRIG2: DAC channel2 software trigger
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2
Bit 0 SWTRIG1: DAC channel1 software trigger
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1
11.5.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
27 26 25
11 10 9
Reserved
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
register value has been loaded into the DAC_DOR2 register.
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
register value has been loaded into the DAC_DOR1 register.
27 26 25
11 10 9
rw rw rw
These bits are written by software which specifies 12-bit data for DAC channel1.
24 23 22 21
Reserved
8 7 6 5
24 23 22
Reserved
8 7 6
DACC1DHR[11:0]
rw rw rw
RM0033 Rev 8
Digital-to-analog converter (DAC)
20 19 18
4 3 2
SWTRIG2 SWTRIG1
21 20 19 18
5 4 3 2
rw rw rw rw
17 16
1 0
w w
17 16
1 0
rw rw
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