Adc Injected Data Register X (Adc_Jdrx) (X= 1; Adc Regular Data Register (Adc_Dr) - ST STM32F205 series Reference Manual

RM0033

10.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)

Address offset: 0x3C - 0x48
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data

10.13.14 ADC regular data register (ADC_DR)

Address offset: 0x4C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Regular data
27 26 25
11 10 9
r r r r
These bits are read-only. They contain the conversion result from injected channel x. The
data are left -or right-aligned as shown in
27 26 25
11 10 9
r r r r
These bits are read-only. They contain the conversion result from the regular
channels. The data are left- or right-aligned as shown in
Figure 33.
24 23 22
Reserved
8 7 6
JDATA[15:0]
r r r
Figure 32
24 23 22
Reserved
8 7 6
DATA[15:0]
r r r
RM0033 Rev 8
Analog-to-digital converter (ADC)
21 20 19 18
5 4 3 2
r r r r
and Figure 33.
21 20 19 18
5 4 3 2
r r r r
Figure 32
17 16
1 0
r r
17 16
1 0
r r
and
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