Intel Agilex Configuration Details; Intel Agilex Configuration Timing Diagram - Intel Agilex Configuration User Manual

UG-20205 | 2019.04.03
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2. Intel Agilex Configuration Details

2.1. Intel Agilex Configuration Timing Diagram

Figure 4. Configuration, Reconfiguration, and Error Timing Diagram
Data[<n>-1:0] (Generic)
AVST_READY (Avalon-ST only)
AVST_VALID (Avalon-ST only)
AS_nCS0 (AS only)
Power_Supply_Status[7:0]
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Power On Reset
nCONFIG
(weak internal or
nSTATUS
external pullup)
CONF_DONE
INIT_DONE
This internal signal is available after CONF_DONE
goes high in designs that include the Reset Release IP.
1
Sample
MSEL[2:0]
2
Power On SDM Start Idle
Config_State
Group 1 Group 2 Group 3
Supply Up Supply Up Supply Up
Reconfiguration Triggered
3
4
User Mode
5
Configuration Initialization User Mode
Reconfiguration Configuration Error
4 3
1
3 5
1
2 2
Device Clean Idle Configuration Err Idle
Grp 3
Grp 2
Down Down
Power Down
Group 1
Down
ISO
9001:2015
Registered