Intel Agilex Lvds Serdes Source-Synchronous Timing Budget; Transmitter Channel-To-Channel Skew - Intel Agilex User Manual

In soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an
optimal DPA clock phase to sample the data. This clock is used for bit slip operation
and deserialization. The DPA block also forwards the selected DPA clock, divided by
the deserialization factor called
deserialized data. This clock signal is put on the periphery clock (PCLK) network.
If you use the soft-CDR mode, do not assert the
has trained. The DPA continuously chooses new phase taps from the PLL to track parts
per million (PPM) differences between the reference clock and incoming data.
In soft-CDR mode, the
continuously changes its phase to track PPM differences between the upstream
transmitter and the local receiver input reference clocks. However, you can use the
rx_dpa_locked
the DPA has selected the optimal phase tap to capture the data. The
signal is expected to deassert when operating in soft-CDR mode. The parallel clock,
rx_coreclock
Note: In soft-CDR mode, you must place all receiver channels of an SERDES instance in one
I/O sub-bank. Top I/O sub-bank can support up to 4 soft-CDR channels and bottom
sub-bank can support up to 8 soft-CDR channels.Refer to Intel Agilex device pin-out
files to identify the pin locations that support this feature.

5.4. Intel Agilex LVDS SERDES Source-Synchronous Timing Budget

The topics in this section describe the timing budget, waveforms, and specifications for
source-synchronous signaling in the Intel Agilex device family.
The LVDS SERDES enables high-speed transmission of data, resulting in better overall
system performance. To take advantage of fast system performance, you must
analyze the timing for these high-speed signals. Timing analysis for the differential
block is different from traditional synchronous timing analysis techniques.
The basis of the source synchronous timing analysis is the skew between the data and
the clock signals instead of the clock-to-output setup times. High-speed differential
data transmission requires the use of timing parameters provided by IC vendors and is
strongly influenced by board skew, cable skew, and clock jitter.
This section defines the source-synchronous differential data orientation timing
parameters, the timing budget definitions for the Intel Agilex device family, and how
to use these timing parameters to determine the maximum performance of a design.

5.4.1. Transmitter Channel-to-Channel Skew

The receiver skew margin calculation uses the transmitter channel-to-channel skew
(TCCS)—an important parameter based on the Intel Agilex transmitter in a source-
synchronous differential interface:
• TCCS is the difference between the fastest and slowest data output transitions,
including the T
• For SERDES transmitters, the Timing Analyzer provides the TCCS value in the
TCCS report (
shows TCCS values for serial output ports.
• You can also get the TCCS value from the device data sheet.
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Intel Agilex General Purpose I/O and LVDS SERDES User Guide
50
rx_divfwdclk
rx_dpa_locked
signal to determine the initial DPA locking conditions that indicate
, generated by the I/O PLLs, is also forwarded to the FPGA fabric.
variation and clock skew.
CO
) in the Intel Quartus Prime compilation report, which
report_TCCS
5. Intel Agilex High-Speed SERDES I/O Architecture
, to the FPGA fabric, along with the
rx_dpa_reset
signal is not valid because the DPA
UG-20214 | 2019.04.02
port after the DPA
rx_dpa_locked
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