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Texas Instruments AM1802 manual available for free PDF download: Reference Manual
Texas Instruments AM1802 Reference Manual (250 pages)
ARM Microprocessor System
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 1.23 MB
Table of Contents
Table of Contents
3
Preface
19
Overview
21
Introduction
22
Block Diagram
22
ARM Subsystem
22
AM1802 ARM Microprocessor Block Diagram
22
ARM Subsystem
23
Chapter 2
24
Introduction
24
Operating States/Modes
25
Processor Status Registers
25
Exceptions and Exception Vectors
26
Exception Vector Table for ARM
26
The 16-BIS/32-BIS Concept
27
16-BIS/32-BIS Advantages
27
Co-Processor 15 (CP15)
28
Addresses in an ARM926EJ-S System
28
Memory Management Unit
28
Different Address Types in ARM System
28
Caches and Write Buffer
29
System Interconnect
31
Introduction
32
AM1802 ARM Microprocessor System Interconnect Matrix
32
System Interconnect Block Diagram
33
System Memory
35
Peripherals
35
Introduction
36
ARM Memories
36
On-Chip RAM Memory
36
External Memories
36
Internal Peripherals
36
Peripherals
36
Memory Protection Unit (MPU)
37
Introduction
38
Purpose of the MPU
38
Features
38
Block Diagram
38
MPU Block Diagram
38
MPU Default Configuration
39
Architecture
39
Privilege Levels
39
MPU Memory Regions
39
Memory Protection Ranges
40
Permission Structures
40
Permission Fields
40
Device Master Settings
40
Request Type Access Controls
41
Protection Check
42
MPU Register Protection
42
Invalid Accesses and Exceptions
42
Reset Considerations
42
Interrupt Support
43
Emulation Considerations
43
MPU_BOOTCFG_ERR Interrupt Sources
43
MPU Registers
44
Memory Protection Unit 1 (MPU1) Registers
44
Memory Protection Unit 2 (MPU2) Registers
44
Configuration Register (CONFIG)
46
Configuration Register (CONFIG) Field Descriptions
46
Revision ID Register (REVID)
46
Revision ID Register (REVID) Field Descriptions
46
Revision Identification Register (REVID)
46
Interrupt Raw Status/Set Register (IRAWSTAT)
47
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
47
Interrupt Enable Status/Clear Register (IENSTAT)
48
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
48
Interrupt Enable Clear Register (IENCLR)
49
Interrupt Enable Clear Register (IENCLR) Field Descriptions
49
Interrupt Enable Set Register (IENSET)
49
Interrupt Enable Set Register (IENSET) Field Descriptions
49
Fixed Range End Address Register (FXD_MPEAR)
50
Fixed Range Start Address Register (FXD_MPSAR)
50
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
51
Programmable Range N Start Address Registers (Progn_Mpsar)
52
Programmable Range N End Address Registers (Progn_Mpear)
53
Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)
54
Fault Address Register (FLTADDRR)
55
Fault Address Register (FLTADDRR) Field Descriptions
55
Fault Status Register (FLTSTAT)
56
Fault Status Register (FLTSTAT) Field Descriptions
56
Fault Clear Register (FLTCLR)
57
Fault Clear Register (FLTCLR) Field Descriptions
57
Device Clocking
59
Overview
60
Device Clock Inputs
60
System Clock Domains
60
Overall Clocking Diagram
61
Frequency Flexibility
62
Peripheral Clocking
63
USB Clocking
63
USB Clocking Diagram
63
Example PLL Frequencies
63
USB Clock Multiplexing Options
63
Ddr2/Mddr Memory Controller Clocking
64
Ddr2/Mddr Memory Controller Clocking Diagram
65
Ddr2/Mddr Memory Controller MCLK Frequencies
65
EMIFA Clocking
66
EMIFA Clocking Diagram
66
EMIFA Frequencies
66
EMAC Clocking
67
EMAC Clocking Diagram
67
Mcasp Clocking
68
Mcasp Clocking Diagram
68
EMAC Reference Clock Frequencies
68
I/O Domains
69
Phase-Locked Loop Controller (PLLC)
71
Introduction
72
PLL Controllers
72
PLLC Structure
73
Device Clock Generation
74
System PLLC Output Clocks
74
Steps for Programming the Plls
75
PLLC Registers
77
PLL Controller 0 (PLLC0) Registers
77
PLL Controller 1 (PLLC1) Registers
78
PLLC0 Revision Identification Register (REVID)
78
PLLC0 Revision Identification Register (REVID) Field Descriptions
78
PLLC1 Revision Identification Register (REVID)
79
PLLC1 Revision Identification Register (REVID) Field Descriptions
79
Reset Type Status Register (RSTYPE)
79
Reset Type Status Register (RSTYPE) Field Descriptions
79
PLLC0 Reset Control Register (RSCTRL)
80
Reset Control Register (RSCTRL)
80
Reset Control Register (RSCTRL) Field Descriptions
80
PLLC0 Control Register (PLLCTL)
81
PLLC0 Control Register (PLLCTL) Field Descriptions
81
PLLC1 Control Register (PLLCTL)
82
PLLC1 Control Register (PLLCTL) Field Descriptions
82
PLLC0 OBSCLK Select Register (OCSEL)
83
PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions
83
PLLC1 OBSCLK Select Register (OCSEL)
84
PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions
84
PLL Multiplier Control Register (PLLM)
85
PLL Multiplier Control Register (PLLM) Field Descriptions
85
PLLC0 Pre-Divider Control Register (PREDIV)
85
PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
85
PLLC0 Divider 1 Register (PLLDIV1)
86
PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions
86
PLLC1 Divider 1 Register (PLLDIV1)
86
PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions
86
PLLC0 Divider 2 Register (PLLDIV2)
87
PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions
87
PLLC1 Divider 2 Register (PLLDIV2)
87
PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions
87
PLLC0 Divider 3 Register (PLLDIV3)
88
PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions
88
PLLC1 Divider 3 Register (PLLDIV3)
88
PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions
88
PLLC0 Divider 4 Register (PLLDIV4)
89
PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions
89
PLLC0 Divider 5 Register (PLLDIV5)
89
PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions
89
PLLC0 Divider 6 Register (PLLDIV6)
90
PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions
90
PLLC0 Divider 7 Register (PLLDIV7)
90
PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions
90
PLLC0 Oscillator Divider 1 Register (OSCDIV)
91
PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
91
PLLC1 Oscillator Divider 1 Register (OSCDIV)
91
PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
91
PLL Controller Command Register (PLLCMD)
92
PLL Controller Command Register (PLLCMD) Field Descriptions
92
PLL Post-Divider Control Register (POSTDIV)
92
PLL Post-Divider Control Register (POSTDIV) Field Descriptions
92
PLL Controller Status Register (PLLSTAT)
93
PLL Controller Status Register (PLLSTAT) Field Descriptions
93
PLLC0 Clock Align Control Register (ALNCTL)
94
PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions
94
PLLC1 Clock Align Control Register (ALNCTL)
95
PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions
95
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
96
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
96
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
97
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
97
PLLC0 Clock Enable Control Register (CKEN)
98
PLLC0 Clock Enable Control Register (CKEN) Field Descriptions
98
PLLC1 Clock Enable Control Register (CKEN)
98
PLLC1 Clock Enable Control Register (CKEN) Field Descriptions
98
PLLC0 Clock Status Register (CKSTAT)
99
PLLC0 Clock Status Register (CKSTAT) Field Descriptions
99
PLLC1 Clock Status Register (CKSTAT)
100
PLLC1 Clock Status Register (CKSTAT) Field Descriptions
100
PLLC0 SYSCLK Status Register (SYSTAT)
101
PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions
101
PLLC1 SYSCLK Status Register (SYSTAT)
102
PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions
102
Emulation Performance Counter 0 Register (EMUCNT0)
103
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
103
Emulation Performance Counter 1 Register (EMUCNT1)
103
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
103
Power and Sleep Controller (PSC)
105
Chapter 8
106
Introduction
106
Power Domain and Module Topology
106
Module States
106
PSC0 Default Module Configuration
106
PSC1 Default Module Configuration
107
Module States
108
Power Domain States
108
Executing State Transitions
110
Power Domain State Transitions
110
Module State Transitions
110
Icepick Emulation Support in the PSC
111
PSC Interrupts
111
Interrupt Events
111
Icepick Emulation Commands
111
PSC Interrupt Events
111
Interrupt Registers
112
Interrupt Handling
113
PSC Registers
114
Power and Sleep Controller 0 (PSC0) Registers
114
Power and Sleep Controller 1 (PSC1) Registers
114
Interrupt Evaluation Register (INTEVAL)
115
Interrupt Evaluation Register (INTEVAL) Field Descriptions
115
Revision Identification Register (REVID)
115
Revision Identification Register (REVID) Field Descriptions
115
PSC0 Module Error Pending Register 0 (MERRPR0)
116
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
116
PSC0 Module Error Pending Register 0 (Modules 0-15) (MERRPR0)
116
PSC1 Module Error Pending Register 0 (MERRPR0)
116
PSC1 Module Error Pending Register 0 (Modules 0-31) (MERRPR0)
116
PSC0 Module Error Clear Register 0 (MERRCR0)
117
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
117
PSC0 Module Error Clear Register 0 (Modules 0-15) (MERRCR0)
117
PSC1 Module Error Clear Register 0 (MERRCR0)
117
PSC1 Module Error Clear Register 0 (Modules 0-31) (MERRCR0)
117
Power Error Clear Register (PERRCR)
118
Power Error Clear Register (PERRCR) Field Descriptions
118
Power Error Pending Register (PERRPR)
118
Power Error Pending Register (PERRPR) Field Descriptions
118
Power Domain Transition Command Register (PTCMD)
119
Power Domain Transition Command Register (PTCMD) Field Descriptions
119
Power Domain Transition Status Register (PTSTAT)
120
Power Domain Transition Status Register (PTSTAT) Field Descriptions
120
Power Domain 0 Status Register (PDSTAT0)
121
Power Domain 0 Status Register (PDSTAT0) Field Descriptions
121
Power Domain 1 Status Register (PDSTAT1)
122
Power Domain 1 Status Register (PDSTAT1) Field Descriptions
122
Power Domain 0 Control Register (PDCTL0)
123
Power Domain 0 Control Register (PDCTL0) Field Descriptions
123
Power Domain 1 Control Register (PDCTL1)
124
Power Domain 1 Control Register (PDCTL1) Field Descriptions
124
Power Domain 0 Configuration Register (PDCFG0)
125
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
125
Power Domain 1 Configuration Register (PDCFG1)
126
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
126
Module Status N Register (Mdstatn)
127
Module Status N Register (Mdstatn) Field Descriptions
127
PSC0 Module Control N Register (Mdctln)
128
PSC0 Module Control N Register (Mdctln) Field Descriptions
128
PSC0 Module Control N Register (Modules 0-15) (Mdctln)
128
PSC1 Module Control N Register (Mdctln)
129
PSC1 Module Control N Register (Mdctln) Field Descriptions
129
PSC1 Module Control N Register (Modules 0-31) (Mdctln)
129
Power Management
131
Introduction
132
Power Consumption Overview
132
PSC and PLLC Overview
132
Features
133
Power Management Features
133
Clock Management
134
Module Clock ON/OFF
134
Module Clock Frequency Scaling
134
PLL Bypass and Power down
134
ARM Sleep Mode Management
135
ARM Wait-For-Interrupt Sleep Mode
135
ARM Clock off
136
ARM Subsystem Clock on
136
RTC-Only Mode
137
Dynamic Voltage and Frequency Scaling (DVFS)
137
Frequency Scaling Considerations
138
Voltage Scaling Considerations
138
Deep Sleep Mode
139
Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up
139
Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up
140
Deep Sleep Sequence
141
Deep Sleep Mode Sequence
141
Entering/Exiting Deep Sleep Mode Using Software Handshaking
142
Additional Peripheral Power Management Considerations
142
USB PHY Power down Control
142
Ddr2/Mddr Memory Controller Clock Gating and Self-Refresh Mode
143
LVCMOS I/O Buffer Receiver Disable
143
Pull-Up/Pull-Down Disable
143
System Configuration (SYSCFG) Module
145
Introduction
146
Protection
146
Privilege Mode Protection
146
Kicker Mechanism Protection
147
Master Priority Control
147
Master Ids
147
SYSCFG Registers
148
Default Master Priority
148
System Configuration Module 0 (SYSCFG0) Registers
148
System Configuration Module 1 (SYSCFG1) Registers
149
Device Identification Register 0 (DEVIDR0)
150
Device Identification Register 0 (DEVIDR0) Field Descriptions
150
Revision Identification Register (REVID)
150
Revision Identification Register (REVID) Field Descriptions
150
Boot Configuration Register (BOOTCFG)
151
Boot Configuration Register (BOOTCFG) Field Descriptions
151
Kick 0 Register (KICK0R)
152
Kick 0 Register (KICK0R) Field Descriptions
152
Kick 1 Register (KICK1R)
152
Kick 1 Register (KICK1R) Field Descriptions
152
Kick Registers (KICK0R-KICK1R)
152
Host 0 Configuration Register (HOST0CFG)
153
Host 0 Configuration Register (HOST0CFG) Field Descriptions
153
Interrupt Raw Status/Set Register (IRAWSTAT)
154
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
154
Interrupt Registers
154
Interrupt Enable Status/Clear Register (IENSTAT)
155
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
155
Interrupt Enable Clear Register (IENCLR)
156
Interrupt Enable Clear Register (IENCLR) Field Descriptions
156
Interrupt Enable Register (IENSET)
156
Interrupt Enable Register (IENSET) Field Descriptions
156
End of Interrupt Register (EOI)
157
End of Interrupt Register (EOI) Field Descriptions
157
Fault Address Register (FLTADDRR)
157
Fault Address Register (FLTADDRR) Field Descriptions
157
Fault Registers
157
Fault Status Register (FLTSTAT)
158
Fault Status Register (FLTSTAT) Field Descriptions
158
Master Priority 0 Register (MSTPRI0)
159
Master Priority 0 Register (MSTPRI0) Field Descriptions
159
Master Priority Registers (MSTPRI0-MSTPRI2)
159
Master Priority 1 Register (MSTPRI1)
160
Master Priority 1 Register (MSTPRI1) Field Descriptions
160
Master Priority 2 Register (MSTPRI2)
161
Master Priority 2 Register (MSTPRI2) Field Descriptions
161
Pin Multiplexing Control 0 Register (PINMUX0)
162
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
162
Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
162
Pin Multiplexing Control 1 Register (PINMUX1)
164
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
164
Pin Multiplexing Control 2 Register (PINMUX2)
166
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
166
Pin Multiplexing Control 3 Register (PINMUX3)
168
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
168
Pin Multiplexing Control 4 Register (PINMUX4)
170
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
170
Pin Multiplexing Control 5 Register (PINMUX5)
172
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
172
Pin Multiplexing Control 6 Register (PINMUX6)
174
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
174
Pin Multiplexing Control 7 Register (PINMUX7)
176
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
176
Pin Multiplexing Control 8 Register (PINMUX8)
178
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
178
Pin Multiplexing Control 9 Register (PINMUX9)
180
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
180
Pin Multiplexing Control 10 Register (PINMUX10)
182
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
182
Pin Multiplexing Control 11 Register (PINMUX11)
184
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
184
Pin Multiplexing Control 12 Register (PINMUX12)
186
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
186
Pin Multiplexing Control 13 Register (PINMUX13)
188
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
188
Pin Multiplexing Control 14 Register (PINMUX14)
190
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
190
Pin Multiplexing Control 15 Register (PINMUX15)
192
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
192
Pin Multiplexing Control 16 Register (PINMUX16)
193
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
193
Pin Multiplexing Control 17 Register (PINMUX17)
195
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
195
Pin Multiplexing Control 18 Register (PINMUX18)
197
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
197
Pin Multiplexing Control 19 Register (PINMUX19)
199
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
199
Suspend Source Register (SUSPSRC)
201
Suspend Source Register (SUSPSRC) Field Descriptions
201
Chip Signal Register (CHIPSIG)
203
Chip Signal Register (CHIPSIG) Field Descriptions
203
Chip Signal Clear Register (CHIPSIG_CLR)
204
Chip Configuration 0 Register (CFGCHIP0)
205
Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
205
Chip Configuration 1 Register (CFGCHIP1)
206
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
206
Chip Configuration 2 Register (CFGCHIP2)
207
Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
207
Chip Configuration 3 Register (CFGCHIP3)
209
Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
209
Chip Configuration 4 Register (CFGCHIP4)
210
Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
210
VTP I/O Control Register (VTPIO_CTL)
210
VTP I/O Control Register (VTPIO_CTL)
211
DDR Slew Register (DDR_SLEW)
212
Deep Sleep Register (DEEPSLEEP)
213
Pullup/Pulldown Enable Register (PUPD_ENA)
214
Pullup/Pulldown Select Register (PUPD_SEL)
214
Pullup/Pulldown Select Register (PUPD_SEL) Default Values
215
RXACTIVE Control Register (RXACTIVE)
216
RXACTIVE Control Register (RXACTIVE) Field Descriptions
216
ARM Interrupt Controller (AINTC)
217
Introduction
218
Interrupt Mapping
218
AINTC Interrupt Mapping
218
AINTC System Interrupt Assignments
219
AINTC Methodology
221
Interrupt Processing
221
Flow of System Interrupts to Host
221
Interrupt Enabling
222
Interrupt Status Checking
222
Interrupt Channel Mapping
222
Host Interrupt Mapping Interrupts
222
Interrupt Prioritization
223
Interrupt Nesting
223
Interrupt Vectorization
224
Interrupt Status Clearing
225
Interrupt Disabling
225
AINTC Registers
225
ARM Interrupt Controller (AINTC) Registers
225
Revision Identification Register (REVID)
226
Revision Identification Register (REVID) Field Descriptions
226
Control Register (CR)
227
Control Register (CR) Field Descriptions
227
Global Enable Register (GER)
228
Global Enable Register (GER) Field Descriptions
228
Global Nesting Level Register (GNLR)
228
Global Nesting Level Register (GNLR) Field Descriptions
228
System Interrupt Status Indexed Clear Register (SICR)
229
System Interrupt Status Indexed Clear Register (SICR) Field Descriptions
229
System Interrupt Status Indexed Set Register (SISR)
229
System Interrupt Status Indexed Set Register (SISR) Field Descriptions
229
System Interrupt Enable Indexed Clear Register (EICR)
230
System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions
230
System Interrupt Enable Indexed Set Register (EISR)
230
System Interrupt Enable Indexed Set Register (EISR) Field Descriptions
230
Host Interrupt Enable Indexed Clear Register (HIEICR)
231
Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions
231
Host Interrupt Enable Indexed Set Register (HEISR)
231
Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions
231
Host Interrupt Enable Indexed Set Register (HIEISR)
231
Vector Base Register (VBR)
232
Vector Base Register (VBR) Field Descriptions
232
Vector Size Register (VSR)
232
Vector Size Register (VSR) Field Descriptions
232
Global Prioritized Index Register (GPIR)
233
Global Prioritized Index Register (GPIR) Field Descriptions
233
Vector Null Register (VNR)
233
Vector Null Register (VNR) Field Descriptions
233
Global Prioritized Vector Register (GPVR)
234
Global Prioritized Vector Register (GPVR) Field Descriptions
234
System Interrupt Status Raw/Set Register 1 (SRSR1)
234
System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions
234
System Interrupt Status Raw/Set Register 2 (SRSR2)
235
System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions
235
System Interrupt Status Raw/Set Register 3 (SRSR3)
235
System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions
235
System Interrupt Status Enabled/Clear Register 1 (SECR1)
236
System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions
236
System Interrupt Status Raw/Set Register 4 (SRSR4)
236
System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions
236
System Interrupt Status Enabled/Clear Register 2 (SECR2)
237
System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions
237
System Interrupt Status Enabled/Clear Register 3 (SECR3)
237
System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions
237
System Interrupt Enable Set Register 1 (ESR1)
238
System Interrupt Enable Set Register 1 (ESR1) Field Descriptions
238
System Interrupt Status Enabled/Clear Register 4 (SECR4)
238
System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions
238
System Interrupt Enable Set Register 2 (ESR2)
239
System Interrupt Enable Set Register 2 (ESR2) Field Descriptions
239
System Interrupt Enable Set Register 3 (ESR3)
239
System Interrupt Enable Set Register 3 (ESR3) Field Descriptions
239
System Interrupt Enable Clear Register 1 (ECR1)
240
System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions
240
System Interrupt Enable Set Register 4 (ESR4)
240
System Interrupt Enable Set Register 4 (ESR4) Field Descriptions
240
System Interrupt Enable Clear Register 2 (ECR2)
241
System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions
241
System Interrupt Enable Clear Register 3 (ECR3)
241
System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions
241
Channel Map Registers (CMR0-CMR25)
242
Channel Map Registers (Cmrn)
242
Channel Map Registers (Cmrn) Field Descriptions
242
System Interrupt Enable Clear Register 4 (ECR4)
242
System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions
242
Host Interrupt Prioritized Index Register 1 (HIPIR1)
243
Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions
243
Host Interrupt Prioritized Index Register 2 (HIPIR2)
243
Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions
243
Host Interrupt Nesting Level Register 1 (HINLR1)
244
Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions
244
Host Interrupt Nesting Level Register 2 (HINLR2)
244
Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions
244
Host Interrupt Enable Register (HIER)
245
Host Interrupt Enable Register (HIER) Field Descriptions
245
Host Interrupt Prioritized Vector Register 1 (HIPVR1)
246
Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions
246
Host Interrupt Prioritized Vector Register 2 (HIPVR2)
246
Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions
246
Boot Considerations
247
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