Generation Of Dma Interrupt For Channel X From Conditions - Texas Instruments TMS320C6201 Reference Manual

5.10 DMA Channel Condition Determination
Figure 5–13. Generation of DMA Interrupt for Channel x From Conditions
Several condition status flags are available to inform you of significant events
or potential problems in DMA channel operation. These flags reside in the
DMA channel secondary control register.
These registers also provide the means to enable the DMA channels to inter-
rupt the CPU through their corresponding interrupt enable (IE) fields. If a con-
dition flag and its corresponding IE bit are set, that condition is enabled to con-
tribute to the status of the interrupt signal from the associated DMA channel
to the CPU. If the TCINT bit in the DMA channel x primary control register is
set, the logical OR of all enabled conditions forms the DMA_INT x signal.
Otherwise, the DMA_INT x remains inactive. This logic is shown in
Figure 5–13. If selected by the interrupt selector, a low-to-high transition on
that DMA_INT causes an interrupt condition to be latched by the CPU.
The SX COND, WDROP COND, and RDROP COND bits in the DMA channel
secondary control register are treated as warning conditions. If these conditions
are enabled and active, they move the DMA channel from the running to the
pause state, regardless of the value of the TCINT bit.
If a condition bit's associated IE bit is set, that condition bit can be cleared only
by you writing a 0 to it. Otherwise, that condition bit can be cleared automatical-
ly. Writing a 1 to a COND bit has no effect. Thus, you cannot manually force
one of the conditions.
Most bits in this register are cleared at reset. The exception is the interrupt enable
for the block transfer complete event (BLOCK IE), which is set at reset. Thus, by
default, the block transfer complete condition is the only condition that can con-
tribute to the CPU interrupt. Other conditions can be enabled by setting the asso-
ciated IE bit.
SX IE
SX COND
FRAME IE
FRAME COND
LAST IE
LAST COND
BLOCK IE
BLOCK COND
RDROP IE
RDROP COND
WDROP IE
WDROP COND
DMA Channel Condition Determination
TCINT
Direct Memory Access (DMA) Controller
DMA_INTx
5-33