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Summary of Contents for Texas Instruments ADS61B23EVM
- Page 1 ADS61xx and ADS61B23EVM User's Guide Literature Number: SLAU206B September 2007 – Revised April 2008...
- Page 2 SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback...
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Page 3: Table Of Contents
Overview ADS61xx/ADS61B23 EVM Quick-Start Procedure Circuit Description Schematic Diagram ADC Circuit Function TI ADC SPI Control Interface Installing the ADC SPI Control Software Setting Up the EVM for ADC SPI Control Using the TI ADC SPI Interface Software Connecting to FPGA Platforms TSW1100 TSW1200 ADC Evaluation... - Page 4 TI ADC SPC Interface Screen Top Silkscreen Component Side Ground Plane 1 Power Plane 1 Bottom Side EVM Schematic, Sheet 1 EVM Schematic, Sheet 2 EVM Schematic, Sheet 3 EVM Schematic, Sheet 4 EVM Schematic, Sheet 5 Breakout Board Schematic, Sheet 6 Breakout Board Pin Assignments Jumpers Surface-Mount Jumpers...
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Page 5: Overview
Overview This user's guide gives a general overview of the evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. This manual is applicable to the ADS6122, ADS6123, ADS6124, ADS6125, ADS6142, ADS6143, ADS6144, ADS6145, and ADS61B23, which collectively are referred to as ADS61xx and ADS61B23. -
Page 6: Circuit Description
Circuit Description Circuit Description Schematic Diagram The schematic diagram for the EVM is in ADC Circuit Function The following sections describe the function of individual circuits. See the relevant data sheet for device operating characteristics. 2.2.1 ADC Operational Mode By default, the ADC is configured to operate in parallel-mode operation, because jumper (J3) asserts a 3.3-V state to the ADC reset pin. - Page 7 www.ti.com Note that the THS4509 used on this EVM is pinout compatible with the THS4508, THS4511, THS4513, and THS4520. Users can easily interchange the amplifier on this EVM and pick the appropriate amplifier based on common-mode range, power supplies, and frequency of operation. Contact your local Texas Instruments (TI) sales representative for assistance in selection of these amplifiers.
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Page 8: Breakout Board Pin Assignments
Circuit Description J4 PIN 2.2.6 Jumper Selections The EVM features several jumpers whose functions are described in surface-mount jumpers in cases where either the signal integrity is important or the functions are rarely used. Table 3 summarizes these options. Table 1. Breakout Board Pin Assignments ADS6122/23/B23/24/25 ADS6142/43/44/45 DESCRIPTION DESCRIPTION... -
Page 9: Jumpers
www.ti.com Description Reference Designator Parallel mode: SEN pin voltage bias SEN control ADC control mode Parallel mode: SCLK pin voltage bias ADS61xx/ADS61B23 power down SDATA control SCLK control Description Reference Designator Clock input path selection Clock input path selection Clock input path selection Analog input path Analog input path THS4509 power down... -
Page 10: Ti Adc Spi Control Interface
TI ADC SPI Control Interface TI ADC SPI Control Interface This section describes the software features accompanying the EVM kit. The TI ADC SPI control software provides full control of the SPI interface, allowing users to write to any of the ADC registers found in the ADC data sheet. -
Page 11: Setting Up The Evm For Adc Spi Control
www.ti.com Setting Up the EVM for ADC SPI Control Users who wish to use the ADC SPI interface must supply 5 VDC to J20, which provides power to the USB circuit. By default, the EVM comes with the ADC configured in parallel mode. In order to use the SPI interface to control the ADC modes of operation, users must move several jumpers. -
Page 12: Ads61Xx Frequently Used Registers
TI ADC SPI Control Interface Default Value ADS61xx Reset 2s Complement CMOS Powerdown: OFF No Course Gain INT Reference Bit-Wise (LVDS Only) Test Mode: None Table 4. ADS61xx Frequently Used Registers Straight Binary DDR LVDS Powerdown On 3.5-dB Course Gain EXT Reference Byte-Wise Multiple Options... -
Page 13: Connecting To Fpga Platforms
www.ti.com Connecting to FPGA Platforms The ADS61xx/ADS61B23 EVM provides several connection options to mate the EVM to various FPGA development platforms and FPGA-based capture boards. TSW1100 Using the accompanying CMOS breakout board, users can easily mate TI's the ADS61xx/ADS61B23 EVM. Simply connect the breakout board to the J2 (Channel 2) connector on the TSW1100. -
Page 14: Adc Evaluation
ADC Evaluation ADC Evaluation This section describes how to set up a typical ADC evaluation system that is similar to what TI uses to perform testing for data-sheet generation. Consequently, the information in this section is generic in nature and is applicable to all high-speed, high-resolution ADC evaluations. This section covers signal tone analysis, which yields ADC data-sheet figures of merit such as signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). -
Page 15: Coherent Input Frequency Selection
www.ti.com Coherent Input Frequency Selection Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fourier transform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that the signal must be continuous-time; however, this is impractical when looking at a finite set of ADC samples, usually collected from a logic analyzer. -
Page 16: Physical Description
Physical Description Physical Description This section describes the physical characteristics and PCB layout of the EVM. PCB Layout The EVM is constructed on a four-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are shown in Figure 2 through performance can be obtained with careful layout using a common ground plane. -
Page 17: Component Side
Physical Description www.ti.com Figure 3. Component Side SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback... -
Page 18: Ground Plane
Physical Description www.ti.com Figure 4. Ground Plane 1 SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback... -
Page 19: Power Plane
Physical Description www.ti.com Figure 5. Power Plane 1 SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback... -
Page 20: Bottom Side
Physical Description www.ti.com Figure 6. Bottom Side SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback... -
Page 21: Bill Of Materials
www.ti.com Bill of Materials Reference Part Installed C1, C5, C8, C52, 33 F C2, C9, C30, C56, 10 F C3, C6, C31 C4, C7, 0.1 F C11–C29,C32–C35, C53, C55, C66, C67, C70, C72,C74, C75, C77–C79,C81, C83, C85, C87–C89, C92 C71, C73, C82, C84 10 F 18 pF 0.22 F... - Page 22 Physical Description Reference Part Installed installed R36, R48 R37, R45 installed R39, R43 69.8 R41, R42 installed 10 k 2.21 k 4.7 k 10 k installed 1.5 k R21, R54, R62–R64 Not installed R55, R56 26.7 R58, R60 R59, R61 82.5 SW PUSHBUTTON TP1, TP3, TP6...
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Page 23: Evm Schematics
www.ti.com EVM Schematics 5 2 3 4 SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback 5 2 3 4 Figure 7. EVM Schematic, Sheet 1 Physical Description... -
Page 24: Evm Schematic, Sheet
Physical Description CLKOUTM CLKOUTP D8_D9_M D8_D9_P D10_D11_M D10_D11_P AVDD_FVDD D12_D13_M CM_REFIN D12_D13_P AVDD AGND AGND Figure 8. EVM Schematic, Sheet 2 www.ti.com SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback... -
Page 25: Evm Schematic, Sheet
www.ti.com SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback ADCCLK- ADCCLK+ VDD0 VDD2 CLKOUT CLKOUT\ VDD0 VDD2 5 2 3 4 Figure 9. EVM Schematic, Sheet 3 Physical Description... -
Page 26: Evm Schematic, Sheet
Physical Description D12_D13_P D12_D13_M D10_D11_P D10_D11_M D8_D9_P D8_D9_M CLKOUTP CLKOUTM CDC_CLKP CDC_CLKM D6_D7_P D6_D7_M D4_D5_P D4_D5_M D2_D3_P D2_D3_M D0_D1_P D0_D1_M CONN_QTH_30X2-D-A CONN_QTH_30X2-D-A Figure 10. EVM Schematic, Sheet 4 www.ti.com FPGA_SEN FPGA_SDATA SH2 FPGA_SCLK SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback... -
Page 27: Evm Schematic, Sheet
www.ti.com SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback Figure 11. EVM Schematic, Sheet 5 Physical Description... -
Page 28: Breakout Board Schematic, Sheet
Physical Description 40PIN IDC 40PIN IDC DATA_OUT DATA_OUT Figure 12. Breakout Board Schematic, Sheet 6 SLAU206B – September 2007 – Revised April 2008 www.ti.com CONN_QSH_30X2-D-A CONN_QSH_30X2-D-A Submit Documentation Feedback... -
Page 29: Evaluation Board/Kit Important Notice
EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. -
Page 30: Important Notice
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
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