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8.5 Interrupts
The ITU has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
8.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when TCNT matches a general register (GR). The compare match
signal is generated in the last state in which the values match (when TCNT is updated from the
matching count to the next count). Therefore, when TCNT matches a general register, the compare
match signal is not generated until the next timer clock input. Figure 8-57 shows the timing of the
setting of IMFA and IMFB.
ø
TCNT input
clock
TCNT
GR
Compare
match signal
IMF
IMI
Figure 8-57 Timing of Setting of IMFA and IMFB by Compare Match
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