Interrupts; Setting Of Status Flags; Figure 8.33 Timing Of Setting Of Imfa And Imfb By Compare Match - Hitachi H8/3062 Hardware Manual

8.5

Interrupts

The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
8.5.1

Setting of Status Flags

Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when 16TCNT matches a general register (GR). The compare
match signal is generated in the last state in which the values match (when 16TCNT is updated
from the matching count to the next count). Therefore, when 16TCNT matches a general register,
the compare match signal is not generated until the next 16TCNT clock input. Figure 8.33 shows
the timing of the setting of IMFA and IMFB.
φ
16TCNT input
clock
16TCNT
GR
Compare
match signal
IMF
IMI

Figure 8.33 Timing of Setting of IMFA and IMFB by Compare Match

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