Interrupts; Setting Of Status Flags - Hitachi H8/3048 Hardware Manual

Single-chip microcomputer

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10.5 Interrupts

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The ITU has two types of interrupts: input capture/compare match interrupts, and overflow

Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a

compare match signal generated when TCNT matches a general register (GR). The compare

match signal is generated in the last state in which the values match (when TCNT is updated from

the matching count to the next count). Therefore, when TCNT matches a general register, the

compare match signal is not generated until the next timer clock input. Figure 10-57 shows the

timing of the setting of IMFA and IMFB.

match signal

Figure 10-57 Timing of Setting of IMFA and IMFB by Compare Match