Exiting Debug Mode - Freescale Semiconductor MSC8144E Reference Manual

Note: The input initiates Debug mode, and the
EE0
indication.
Figure 25-8. Selected SC3400 Core Issues a Debug Request to All Other SC3400 Cores
MSC8144
EE0
Board

25.1.13 Exiting Debug Mode

When an SC3400 core enters Debug mode (this is checked by OCE module status bits through
JTAG as shown in Table 25-2), the
masked, preventing any more debug requests. When all the SC3400 cores exit Debug mode, the
internal signals of all SC3400 cores are unmasked, enabling further debug requests. To
EE0
restart the SC3400 cores, a
completes, the update launches all four SC3400 cores.
Note: When multiple cores are in Debug mode, issuing simultaneous go instructions to such
cores does not guarantee that the cores exit Debug mode on the same clock cycle.
Freescale Semiconductor
EE0
MSC8144
EE1 EE0 EE1
Figure 25-9. Board EE Signal Interconnectivity
internal signal of that SC3400 core OCE module is
EE0
instruction is scanned into all four SC3400 cores. When the scan
go
MSC8144E Reference Manual, Rev. 3
output is the debug acknowledge
EE1
EE1
EE0
EE0
EE0
EE1
EE1
EE1
MSC8144
EE0
TAP, Boundary Scan, and OCE
MSC8144
EE0
SC3400
core
EE1
EE1
25-15