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Freescale Semiconductor MC68HC908MR32 Datasheet

Freescale Semiconductor MC68HC908MR32 Datasheet (282 pages)

Freescale Semiconductor Microcontrollers Data Sheet

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 1 MB

Table of Contents

Revision History
4
Table of Contents
5
Chapter 1 General Description
17
Chapter 2 Memory
25
- Memory
  25
- Introduction
  25
- Unimplemented Memory Locations
  25
- Reserved Memory Locations
  25
- I/O Section
  26
- Memory Map
  26
- Monitor ROM
  37
- Random-Access Memory (RAM)
  37
- FLASH Memory (FLASH)
  38
- FLASH Control Register
  38
- FLASH Page Erase Operation
  39
- FLASH Mass Erase Operation
  40
- FLASH Program Operation
  41
- FLASH Block Protection
  43
- FLASH Block Protect Register
  43
- Wait Mode
  44
- Stop Mode
  44
Chapter 3 Analog-To-Digital Converter (ADC)
45
- Analog-To-Digital Converter (ADC)
  45
- Introduction
  45
- Features
  45
- Functional Description
  45
- ADC Port I/O Pins
  47
- Voltage Conversion
  47
- Conversion Time
  48
- Continuous Conversion
  48
- Result Justification
  48
- Monotonicity
  49
- Interrupts
  50
- Wait Mode
  50
- I/O Signals
  50
- ADC Analog Power Pin
  50
- Ddad )
  50
- ADC Analog Ground Pin
  50
- Ssad )
  50
- ADC Voltage Reference Pin
  50
- Refh )
  50
- ADC Voltage Reference Low Pin
  50
- ADC Voltage in (ADVIN)
  51
- ADC External Connections
  51
- Anx
  51
- VREFH and VREFL
  51
- Grounding
  51
- I/O Registers
  51
- ADC Status and Control Register
  52
- ADC Data Register High
  54
- ADC Data Register Low
  54
- ADC Clock Register
  55
Chapter 4 Clock Generator Module (CGM)
57
- Clock Generator Module (CGM)
  57
- Introduction
  57
- Features
  57
- Functional Description
  57
- Crystal Oscillator Circuit
  59
- Phase-Locked Loop Circuit (PLL)
  59
- PLL Circuits
  59
- Acquisition and Tracking Modes
  60
- Manual and Automatic PLL Bandwidth Modes
  60
- Programming the PLL
  61
- Special Programming Exceptions
  62
- Base Clock Selector Circuit
  62
- CGM External Connections
  63
- I/O Signals
  64
- Crystal Amplifier Input Pin (OSC1)
  64
- Crystal Amplifier Output Pin (OSC2)
  64
- External Filter Capacitor Pin (CGMXFC)
  64
- PLL Analog Power Pin (VDDA )
  64
- Oscillator Enable Signal (SIMOSCEN)
  64
- Crystal Output Frequency Signal (CGMXCLK)
  65
- CGM Base Clock Output (CGMOUT)
  65
- CGM CPU Interrupt (CGMINT)
  65
- CGM Registers
  65
- PLL Control Register
  66
- PLL Bandwidth Control Register
  67
- PLL Programming Register
  68
- Interrupts
  69
- Wait Mode
  69
- Acquisition/Lock Time Specifications
  70
- Acquisition/Lock Time Definitions
  70
- Parametric Influences on Reaction Time
  70
- Choosing a Filter Capacitor
  71
- Reaction Time Calculation
  71
Chapter 5 Configuration Register (CONFIG)
73
- Introduction
  73
- Functional Description
  73
- Configuration Register
  74
Chapter 6 Computer Operating Properly (COP)
75
- Computer Operating Properly (COP)
  75
- Introduction
  75
- Functional Description
  75
- I/O Signals
  76
- Cgmxclk
  76
- COPCTL Write
  76
- Power-On Reset
  76
- Internal Reset
  76
- Reset Vector Fetch
  76
- COPD (COP Disable)
  77
- COP Control Register
  77
- Interrupts
  77
- Monitor Mode
  77
- Wait Mode
  77
- Stop Mode
  77
Chapter 7 Central Processor Unit (CPU)
79
- Central Processor Unit (CPU)
  79
- Introduction
  79
- Features
  79
- CPU Registers
  79
- Accumulator
  80
- Index Register
  80
- Stack Pointer
  81
- Program Counter
  81
- Condition Code Register
  82
- Arithmetic/Logic Unit (ALU)
  83
- Low-Power Modes
  83
- Wait Mode
  83
- Stop Mode
  83
- CPU During Break Interrupts
  83
- Instruction Set Summary
  84
- Opcode Map
  89
Chapter 8 External Interrupt (IRQ)
91
- External Interrupt (IRQ)
  91
- Introduction
  91
- Features
  91
- Functional Description
  91
- IRQ Pin
  92
- IRQ Status and Control Register
  94
Chapter 9 Low-Voltage Inhibit (LVI)
97
- Low-Voltage Inhibit (LVI)
  97
- Introduction
  97
- Features
  97
- Functional Description
  97
- Polled LVI Operation
  98
- Forced Reset Operation
  98
- False Reset Protection
  98
- LVI Trip Selection
  98
- LVI Status and Control Register
  99
- LVI Interrupts
  99
- Wait Mode
  99
- Stop Mode
  100
Chapter 10 Input/Output (I/O) Ports (PORTS)
101
- Input/Output (I/O) Ports (PORTS)
  101
- Introduction
  101
- Port a
  103
- Port a Data Register
  103
- Data Direction Register a
  103
- Port B
  104
- Port B Data Register
  104
- Data Direction Register B
  105
- Port C
  106
- Port C Data Register
  106
- Data Direction Register C
  106
- Port D
  107
- Port E
  108
- Port E Data Register
  108
- Data Direction Register E
  109
- Port F
  110
- Port F Data Register
  110
- Data Direction Register F
  110
Chapter 11 Power-On Reset (POR)
113
- Power-On Reset (POR)
  113
- Introduction
  113
- Functional Description
  113
Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC)
115
- Pulse-Width Modulator for Motor Control (PWMMC)
  115
- Introduction
  115
- Features
  115
- Timebase
  120
- Resolution
  120
- Prescaler
  122
- PWM Generators
  122
- Load Operation
  122
- PWM Data Overflow and Underflow Conditions
  125
- Output Control
  126
- Selecting Six Independent Pwms or Three Complementary PWM Pairs
  126
- Dead-Time Insertion
  127
- Top/Bottom Correction with Motor Phase Current Polarity Sensing
  130
- Output Polarity
  133
- PWM Output Port Control
  135
- Fault Protection
  137
- Fault Condition Input Pins
  137
- Fault Pin Filter
  139
- Automatic Mode
  139
- Manual Mode
  140
- Software Output Disable
  141
- Output Port Control
  141
- Initialization and the PWMEN Bit
  142
- PWM Operation in Wait Mode
  143
- Control Logic Block
  143
- PWM Counter Registers
  143
- PWM Counter Modulo Registers
  144
- Pwmx Value Registers
  145
- PWM Control Register 1
  146
- PWM Control Register 2
  148
- Dead-Time Write-Once Register
  150
- PWM Disable Mapping Write-Once Register
  150
- Fault Control Register
  150
- Fault Status Register
  152
- Fault Acknowledge Register
  153
- PWM Output Control Register
  154
- PWM Glossary
  155
Chapter 13 Serial Communications Interface Module (SCI)
157
- Serial Communications Interface Module (SCI)
  157
- Introduction
  157
- Features
  157
- Functional Description
  159
- Data Format
  160
- Transmitter
  161
- Character Length
  162
- Character Transmission
  162
- Break Characters
  162
- Idle Characters
  163
- Inversion of Transmitted Output
  163
- Transmitter Interrupts
  163
- Receiver
  163
- Character Length
  164
- Character Reception
  165
- Data Sampling
  165
- Framing Errors
  167
- Receiver Wakeup
  167
- Receiver Interrupts
  167
- Error Interrupts
  167
- Wait Mode
  168
- SCI During Break Module Interrupts
  168
- I/O Signals
  168
- Ptf5/Txd (Transmit Data)
  168
- Ptf4/Rxd (Receive Data)
  169
- I/O Registers
  169
- SCI Control Register 1
  169
- SCI Control Register 2
  171
- SCI Control Register 3
  173
- SCI Status Register 1
  174
- SCI Status Register 2
  176
- SCI Data Register
  177
- SCI Baud Rate Register
  177
Chapter 14 System Integration Module (SIM)
181
- System Integration Module (SIM)
  181
- Introduction
  181
- SIM Bus Clock Control and Generation
  182
- Bus Timing
  182
- Clock Startup from por or LVI Reset
  182
- Clocks in Wait Mode
  183
- Reset and System Initialization
  183
- External Pin Reset
  183
- Active Resets from Internal Sources
  184
- Power-On Reset (POR)
  185
- Computer Operating Properly (COP) Reset
  185
- Illegal Opcode Reset
  186
- Illegal Address Reset
  186
- Forced Monitor Mode Entry Reset (MENRST)
  186
- Low-Voltage Inhibit (LVI) Reset
  186
- SIM Counter
  186
- SIM Counter During Power-On Reset
  186
- SIM Counter and Reset States
  186
- Exception Control
  187
- Interrupts
  187
- Hardware Interrupts
  189
- Software Interrupt (SWI) Instruction
  190
- Reset
  190
- Low-Power Mode
  190
- Wait Mode
  190
- Stop Mode
  191
- SIM Registers
  191
- SIM Break Status Register
  191
- SIM Reset Status Register
  192
- SIM Break Flag Control Register
  193
Chapter 15 Serial Peripheral Interface Module (SPI)
195
- Serial Peripheral Interface Module (SPI)
  195
- Introduction
  195
- Features
  195
- Pin Name Conventions
  195
- Functional Description
  197
- Master Mode
  198
- Slave Mode
  199
- Transmission Formats
  199
- Clock Phase and Polarity Controls
  199
- Transmission Format When CPHA = 0
  200
- Transmission Format When CPHA = 1
  201
- Transmission Initiation Latency
  201
- Error Conditions
  203
- Overflow Error
  203
- Mode Fault Error
  204
- Interrupts
  206
- Resetting the SPI
  207
- Queuing Transmission Data
  207
- Low-Power Mode
  208
- I/O Signals
  208
- MISO (Master In/Slave Out)
  209
- MOSI (Master Out/Slave In)
  209
- SPSCK (Serial Clock)
  209
- SS (Slave Select)
  209
- VSS (Clock Ground)
  210
- I/O Registers
  210
- SPI Control Register
  210
- SPI Status and Control Register
  212
- SPI Data Register
  214
Chapter 16 Timer Interface a (TIMA)
215
- Timer Interface a (TIMA)
  215
- Introduction
  215
- Features
  215
- Functional Description
  219
- TIMA Counter Prescaler
  219
- Input Capture
  219
- Output Compare
  220
- Unbuffered Output Compare
  220
- Buffered Output Compare
  221
- Pulse-Width Modulation (PWM)
  221
- Unbuffered PWM Signal Generation
  222
- Buffered PWM Signal Generation
  223
- PWM Initialization
  223
- Interrupts
  224
- Wait Mode
  224
- I/O Signals
  225
- TIMA Clock Pin (PTE3/TCLKA)
  225
- TIMA Channel I/O Pins (PTE4/TCH0A-PTE7/TCH3A)
  225
- I/O Registers
  225
- TIMA Status and Control Register
  225
- TIMA Counter Registers
  227
- TIMA Counter Modulo Registers
  228
- TIMA Channel Status and Control Registers
  228
- TIMA Channel Registers
  232
Chapter 17 Timer Interface B (TIMB)
235
- Timer Interface B (TIMB)
  235
- Introduction
  235
- Features
  235
- Functional Description
  235
- TIMB Counter Prescaler
  238
- Input Capture
  238
- Output Compare
  239
- Unbuffered Output Compare
  239
- Buffered Output Compare
  240
- Pulse-Width Modulation (PWM)
  240
- Unbuffered PWM Signal Generation
  241
- Buffered PWM Signal Generation
  241
- PWM Initialization
  242
- Interrupts
  243
- Wait Mode
  243
- I/O Signals
  243
- TIMB Clock Pin (PTE0/TCLKB)
  243
- TIMB Channel I/O Pins (PTE1/TCH0B-PTE2/TCH1B)
  243
- I/O Registers
  244
- TIMB Status and Control Register
  244
- TIMB Counter Registers
  246
- TIMB Counter Modulo Registers
  246
- TIMB Channel Status and Control Registers
  247
- TIMB Channel Registers
  250
Chapter 18 Development Support
251
- Development Support
  251
- Introduction
  251
- Break Module (BRK)
  251
- Functional Description
  251
- Flag Protection During Break Interrupts
  251
- CPU During Break Interrupts
  253
- TIM1 and TIM2 During Break Interrupts
  253
- COP During Break Interrupts
  253
- Low-Power Modes
  253
- Wait Mode
  253
- Stop Mode
  253
- Break Module Registers
  253
- Break Status and Control Register
  254
- Break Address Registers
  254
- Break Status Register
  255
- Break Flag Control Register
  255
- Monitor ROM (MON)
  255
- Functional Description
  256
- Entering Monitor Mode
  256
- Normal Monitor Mode
  256
- Forced Monitor Mode
  259
- Data Format
  259
- Echoing
  260
- Break Signal
  260
- Commands
  260
- Baud Rate
  263
- Security
  263
Chapter 19 Electrical Specifications
265
- Electrical Specifications
  265
- Introduction
  265
- Absolute Maximum Ratings
  265
- Functional Operating Range
  266
- Thermal Characteristics
  266
- DC Electrical Characteristics
  267
- FLASH Memory Characteristics
  268
- Control Timing
  268
- Serial Peripheral Interface Characteristics
  269
- Timer Interface Module Characteristics
  272
- Clock Generation Module Component Specifications
  272
- CGM Operating Conditions
  272
- CGM Acquisition/Lock Time Specifications
  273
- Analog-To-Digital Converter (ADC) Characteristics
  274
Chapter 20 Ordering Information and Mechanical Specifications
275
- Ordering Information and Mechanical Specifications
  275
- Introduction
  275
- Order Numbers
  275
- 64-Pin Plastic Quad Flat Pack (QFP)
  276
- 56-Pin Shrink Dual In-Line Package (SDIP)
  277
Appendix A MC68HC908MR16
279

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