About The Biu And Write Buffer; Write Buffer Operation - ARM ARM966E-S Technical Reference Manual

Bus Interface Unit
6.1

About the BIU and write buffer

6-2
The ARM966E-S supports an Advanced Microprocessor Bus Architecture (AMBA)
Advanced High-performance Bus (AHB) interface. The AHB is a new generation of
AMBA interface that addresses the requirements of high-performance synthesizable
designs, including:
• single clock edge operation (rising edge)
• unidirectional (nontristate) buses
• burst transfers
• split transactions
• single-cycle bus master handover.
See the AMBA Rev 2.0 AHB specification for full details of this bus architecture.
The ARM966E-S BIU implements a fully-compliant AHB bus master interface and
incorporates a write buffer to increase system performance. The BIU is the link between
the ARM9E-S core with its tightly-coupled SRAM and the external AHB memory. The
AHB memory must be accessed to initialize the tightly-coupled SRAM. The AHB
memory must also be accessed to access code and data that are not assigned to the
tightly-coupled SRAM address space (or if the SRAM is disabled).
When an external AHB access is performed, the BIU and the system controller
handshake to ensure that the ARM9E-S core is stalled. If the write buffer is used, it
might be possible to allow the core to continue program execution. The BIU is
responsible for controlling the write buffer and related stall behavior (see Write buffer
operation on page 6-3).
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