Memory Map - Fujitsu FR60 Hardware Manual

3.8

Memory Map

This section shows the memory map for the FR family.
■ Memory Map
The address space of memory is 32 bits linear.
Figure 3.8-1 shows the memory map.
0000 0000
0000 0100
0000 0200
0000 0400
000F FC00
000F FFFF
FFFF FFFF
❍ Direct addressing area
The following areas in the address space are the areas for I/O. When direct addressing is used
in these areas, an operand address can be directly specified in an instruction.
The size of an address area for which an address can be directly specified varies is determined
by the data length as follows:
• Byte data (8 bits):
• Halfword data (16 bits): 000
• Word data (32 bits):
❍Vector table initial area
The area from 000FFC00
You can place the vector table that will be used during EIT processing at any address by
rewriting the TBR. Initialization by a reset places the table at this address.
Figure 3.8-1 Memory Map
H
Byte data
H
Halfword data
H
Word data
H
H
Vector table
initial area
H
H
000 to 0FF
H H
to 1FF
H H
000 to 3FF
H H
to 000FFFFF is the initial EIT vector table area.
H H
CHAPTER 3 CPU AND CONTROL UNITS
Direct addressing area
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