Dmac Interrupt Control - Fujitsu FR60 Hardware Manual

14.3.10 DMAC Interrupt Control

Independent of peripheral interrupts that become transfer requests, interrupts can also
be output for each DMAC channel.
■ DMAC Interrupt Control
The following interrupts can be output for each DMAC channel:
• Transfer end interrupt: Occurs only when operation ends normally.
• Error interrupt:
• Error interrupt:
All of these interrupts are output according to the meaning of the end code.
An interrupt request can be cleared by writing "000
Be sure to clear the end code by writing "000
If reloading is enabled, the transfer is automatically restarted. At this point, however, the end
code is not cleared and is retained until a new end code is written when the next transfer ends.
Since only one end source can be displayed in an end code, the result after considering the
order of priority is displayed when multiple sources occur simultaneously. The interrupt that
occurs at this point conforms to the displayed end code.
The following shows the priority for displaying end codes (in order of decreasing priority):
• Reset
• Clearing by writing "000
• Peripheral stop request or external pin input (DSTP) stop request
• Normal end
• Stopping when address error detected
• Channel selection and control
■ DMA Transfer during Sleep
• The DMAC can also operate in sleep mode.
• If you anticipate operations during sleep mode, note the following:
- Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before
sleep mode is entered.
- The sleep mode is released by an interrupt. Thus, if a peripheral interrupt is selected as
the DMAC start source, interrupts must be disabled by the interrupt controller.
• If you do not want to release sleep mode with a DMAC end interrupt, disable these
interrupts.
Transfer stop request due to a peripheral circuit (error due to a
peripheral)
Occurrence of address error (error due to software)
" before restarting.
B
"
B
CHAPTER 14 DMA CONTROLLER (DMAC)
" to DSS2 to DSS0 (end code) of DMACS.
B
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