■ Serial I/O Prescaler Control Register (CDCR)
The bit configuration of the serial I/O prescaler control register (CDCR) is shown below.
This register must be accessed in byte units.
Address : 000032
The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000032
[Bit 15] Machine clock divide mode select (MD)
The machine clock divide mode select bit is the operation enable bit of the communication prescaler.
[Bits 11 to 8] Divide 3 to divide 0 (DIV3 to DIV0)
The divide 3 to divide 0 bits are used to specify the division ratio for the peripheral system clock
If the division ratio is changed, wait before starting communication until the time equal to the two
divided clock pulses has elapsed for clock stabilization.
Communication prescaler operation is disabled. (Default)
Communication prescaler operation is enabled.
DIV3 to 0
DIV0 Initial value: 0---1111
in the CDCR is