STMicroelectronics STM32F415 Manuals

Manuals and User Guides for STMicroelectronics STM32F415. We have 1 STMicroelectronics STM32F415 manual available for free PDF download: Reference Manual

STMicroelectronics STM32F415 Reference Manual (1731 pages)

advanced ARM-based 32-bit MCUs

Brand: STMicroelectronics | Category: Controller | Size: 24 MB

Table of Contents
2
Documentation Conventions

57
- List of Abbreviations for Registers
  57
- Glossary
  58
- Peripheral Availability
  58
Memory and Bus Architecture

59
- System Architecture
  59
  - Figure 1. System Architecture for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx Devices
    60
  - D-Bus
    62
  - Figure 2. System Architecture for Stm32F42Xxx and Stm32F43Xxx Devices
    62
  - I-Bus
    62
  - S-Bus
    62
  - Busmatrix
    63
  - DMA Memory Bus
    63
  - DMA Peripheral Bus
    63
  - DMA2D Bus
    63
  - Ethernet DMA Bus
    63
  - LCD-TFT Controller DMA Bus
    63
  - USB OTG HS DMA Bus
    63
  - AHB/APB Bridges (APB)
    64
- Memory Organization
  64
- Memory Map
  64
  - Table 1
    64
  - Table 1. Stm32F4Xx Register Boundary Addresses
    64
  - Bit Banding
    68
  - Embedded SRAM
    68
  - Flash Memory Overview
    68
- Boot Configuration
  69
- Table 2. Boot Modes
  69
- Table 3. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
  71
- Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F42Xxx and Stm32F43Xxx
  71
Embedded Flash Memory Interface

73
CRC Calculation Unit

113
- CRC Introduction
  113
- CRC Main Features
  113
- Figure 8. CRC Calculation Unit Block Diagram
  113
- CRC Functional Description
  114
- CRC Registers
  114
  - Data Register (CRC_DR)
    114
  - Independent Data Register (CRC_IDR)
    114
  - Control Register (CRC_CR)
    115
  - CRC Register Map
    115
  - Table 21. CRC Calculation Unit Register Map and Reset Values
    115
Power Controller (PWR)

116
Reset and Clock Control for Stm32F42Xxx and Stm32F43Xxx (RCC)

150
Reset and Clock Control for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC)

213
General-Purpose I/Os (GPIO)

269
System Configuration Controller (SYSCFG)

291
Digital-To-Analog Converter (DAC)

435
Digital Camera Interface (DCMI)

457
LCD-TFT Controller (LTDC)

480
Independent Watchdog (IWDG)

699
Window Watchdog (WWDG)

704
Serial Audio Interface (SAI)

919
Transmitter (USART)

958
- USART Functional Description
  959
- PCLK = 8 Mhz or F PCLK = 12 Mhz
  973
  - Oversampling by 8
    974
  - Oversampling by 16
    974
- PCLK = 16 Mhz or F PCLK = 24 Mhz
  974
- USART Interrupts
  998
  - Table 147. USART Mode Configuration
    999
  - Data Register (USART_DR)
    1002
  - Control Register 2 (USART_CR2)
    1005
  - Control Register 3 (USART_CR3)
    1006
  - Guard Time and Prescaler Register (USART_GTPR)
    1009
  - Table 148. USART Register Map and Reset Values
    1010
- SDIO Main Features
  1011
- Figure 321. SDIO "No Response" and "No Data" Operations
  1012
- Figure 322. SDIO (Multiple) Block Read Operation
  1012
- Figure 323. SDIO (Multiple) Block Write Operation
  1013
- Figure 324. SDIO Sequential Read Operation
  1013
- Figure 325. SDIO Sequential Write Operation
  1013
- Figure 326. SDIO Block Diagram
  1014
- SDIO Functional Description
  1014
  - Figure 327. SDIO Adapter
    1015
  - Table 149. SDIO I/O Definitions
    1015
  - Figure 328. Control Unit
    1016
  - Figure 329. SDIO Adapter Command Path
    1017
  - Figure 330. Command Path State Machine (CPSM)
    1018
  - Figure 331. SDIO Command Transfer
    1019
  - Table 150. Command Format
    1019
  - Table 151. Short Response Format
    1020
  - Table 152. Long Response Format
    1020
  - Table 153. Command Path Status Flags
    1020
  - Figure 332. Data Path
    1021
  - Figure 333. Data Path State Machine (DPSM)
    1022
  - Table 154. Data Token Format
    1023
  - Table 155. Transmit FIFO Status Flags
    1024
  - SDIO APB2 Interface
    1025
  - Table 156. Receive FIFO Status Flags
    1025
- Card Functional Description
  1026
  - Card Identification Process
    1027
  - Block Write
    1028
  - Block Read
    1029
  - Erase: Group Erase and Sector Erase
    1031
  - Card Status Register
    1034
  - Table 157. Card Status
    1035
  - SD Status Register
    1037
  - Table 158. SD Status
    1038
  - Table 159. Speed Class Code Field
    1039
  - Table 160. Performance Move Field
    1039
  - Table 161. AU_SIZE Field
    1040
  - Table 162. Maximum au Size
    1040
  - Table 163. Erase Size Field
    1040
  - Table 164. Erase Timeout Field
    1041
  - Table 165. Erase Offset Field
    1041
  - SD I/O Mode
    1041
  - Commands and Responses
    1042
  - Table 166. Block-Oriented Write Commands
    1043
  - Table 167. Block-Oriented Write Protection Commands
    1044
  - Table 168. Erase Commands
    1044
  - Table 169. I/O Mode Commands
    1045
  - Table 170. Lock Card
    1045
  - Table 171. Application-Specific Commands
    1045
  - Table 172. R1 Response
    1046
- Response Formats
  1046
  - R3 (OCR Register)
    1047
  - Table 173. R2 Response
    1047
  - Table 174. R3 Response
    1047
  - Table 175. R4 Response
    1047
  - R5 (Interrupt Request)
    1048
  - Table 176. R4B Response
    1048
  - Table 177. R5 Response
    1048
  - Table 178. R6 Response
    1049
- SDIO I/O Card-Specific Operations
  1049
  - SDIO I/O Read Wait Operation by SDIO_D2 Signaling
    1050
- CE-ATA Specific Operations
  1051
- HW Flow Control
  1052
  - SDI Clock Control Register (SDIO_CLKCR)
    1053
  - SDIO Argument Register (SDIO_ARG)
    1054
  - SDIO Command Register (SDIO_CMD)
    1055
  - Table 179. Response Type and Sdio_Respx Registers
    1056
  - SDIO Command Response Register (SDIO_RESPCMD)
    1056
  - SDIO Data Timer Register (SDIO_DTIMER)
    1057
  - SDIO Data Control Register (SDIO_DCTRL)
    1058
  - SDIO Data Counter Register (SDIO_DCOUNT)
    1059
  - SDIO Status Register (SDIO_STA)
    1060
  - SDIO Interrupt Clear Register (SDIO_ICR)
    1061
  - SDIO Mask Register (SDIO_MASK)
    1063
  - SDIO FIFO Counter Register (SDIO_FIFOCNT)
    1065
  - Table 180. SDIO Register Map
    1066
  - SDIO Data FIFO Register (SDIO_FIFO)
    1066
- Bxcan Introduction
  1068
- Figure 334. CAN Network Topology
  1069
- Bxcan General Description
  1069
  - Control, Status and Configuration Registers
    1070
  - Figure 335. Dual CAN Block Diagram
    1071
- Bxcan Operating Modes
  1071
  - Initialization Mode
    1072
  - Figure 336. Bxcan Operating Modes
    1073
- Test Mode
  1073
- Figure 337. Bxcan in Silent Mode
  1074
- Figure 338. Bxcan in Loop Back Mode
  1074
- Figure 339. Bxcan in Combined Mode
  1075
- Debug Mode
  1075
  - Figure 340. Transmit Mailbox States
    1076
  - Figure 341. Receive FIFO States
    1077
  - Time Triggered Communication Mode
    1077
  - Identifier Filtering
    1078
  - Figure 342. Filter Bank Scale Configuration - Register Organization
    1080
  - Figure 343. Example of Filter Numbering
    1081
  - Figure 344. Filtering Mechanism - Example
    1082
  - Message Storage
    1082
  - Figure 345. CAN Error State Diagram
    1083
  - Table 181. Transmit Mailbox Mapping
    1083
  - Table 182. Receive Mailbox Mapping
    1083
  - Error Management
    1084
  - Figure 346. Bit Timing
    1085
  - Figure 347. CAN Frames
    1086
- Bxcan Interrupts
  1086
- Figure 348. Event Flags and Interrupt Generation
  1087
- CAN Registers
  1088
  - CAN Mailbox Registers
    1098
  - Figure 349. RX and TX Mailboxes
    1098
  - CAN Filter Registers
    1105
  - Table 183. Bxcan Register Map and Reset Values
    1109
DMA Controller

1113
- Ethernet Introduction
  1113
  - MAC Core Features
    1114
  - DMA Features
    1115
  - Table 184. Alternate Function Mapping
    1116
- Ethernet Pins
  1116
- Figure 350. ETH Block Diagram
  1117
- Ethernet Functional Description: SMI, MII and RMII
  1117
  - Figure 351. SMI Interface Signals
    1118
  - Table 185. Management Frame Format
    1118
  - Figure 352. MDIO Timing and Frame Structure - Write Cycle
    1119
  - Figure 353. MDIO Timing and Frame Structure - Read Cycle
    1120
  - Media-Independent Interface: MII
    1120
  - Table 186. Clock Range
    1120
  - Figure 354. Media Independent Interface Signals
    1121
  - Table 187. TX Interface Signal Encoding
    1122
  - Table 188. RX Interface Signal Encoding
    1122
  - Figure 355. MII Clock Sources
    1123
  - Figure 356. Reduced Media-Independent Interface Signals
    1123
  - Reduced Media-Independent Interface: RMII
    1123
  - Figure 357. RMII Clock Sources
    1124
  - Figure 358. Clock Scheme
    1124
  - MII/RMII Selection
    1124
- Ethernet Functional Description: MAC 802.3
  1125
  - Figure 359. Address Field Format
    1126
  - Figure 360. MAC Frame Format
    1128
  - Figure 361. Tagged MAC Frame Format
    1128
  - MAC Frame Transmission
    1129
  - Figure 362. Transmission Bit Order
    1135
  - Figure 363. Transmission with no Collision
    1135
  - Figure 364. Transmission with Collision
    1136
  - Figure 365. Frame Transmission in MMI and RMII Modes
    1136
  - MAC Frame Reception
    1136
  - Table 189. Frame Statuses
    1138
  - Figure 366. Receive Bit Order
    1140
  - Figure 367. Reception with no Error
    1141
  - Figure 368. Reception with Errors
    1141
  - Figure 369. Reception with False Carrier Indication
    1141
  - MAC Interrupts
    1141
  - Figure 370. MAC Core Interrupt Masking Scheme
    1142
  - MAC Filtering
    1142
  - Table 190. Destination Address Filtering
    1144
  - MAC Loopback Mode
    1145
  - Table 191. Source Address Filtering
    1145
  - Power Management: PMT
    1146
  - Figure 371. Wakeup Frame Filter Register
    1147
  - Precision Time Protocol (IEEE1588 PTP)
    1149
  - Figure 372. Networked Time Synchronization
    1150
  - Figure 373. System Time Update Using the Fine Correction Method
    1152
  - Figure 374. PTP Trigger Output to TIM2 ITR1 Connection
    1154
  - Figure 375. PPS Output
    1155
- Ethernet Functional Description: DMA Controller Operation
  1155
- Ethernet Interrupts
  1182
- Ethernet Register Descriptions
  1183
- OTG_FS Introduction
  1233
  - General Features
    1234
  - Figure 386. OTG Full-Speed Block Diagram
    1235
  - Peripheral-Mode Features
    1235
  - OTG Full-Speed Core
    1236
  - Figure 387. OTG A-B Device Connection
    1237
- OTG Dual Role Device (DRD)
  1237
  - SRP Dual Role Device
    1238
  - Figure 388. USB Peripheral-Only Connection
    1239
  - SRP-Capable Peripheral
    1239
  - Peripheral Endpoints
    1240
  - USB Host
    1242
  - Figure 389. USB Host-Only Connection
    1243
  - SRP-Capable Host
    1243
  - Host Channels
    1245
  - Host Scheduler
    1246
  - Figure 390. SOF Connectivity
    1247
- SOF Trigger
  1247
  - Peripheral Sofs
    1248
  - Figure 391. Updating OTG_FS_HFIR Dynamically
    1249
- Dynamic Update of the OTG_FS_HFIR Register
  1249
- Figure 392. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
  1250
- USB Data Fifos
  1250
  - Figure 393. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
    1251
  - Peripheral Tx Fifos
    1251
  - Host Tx Fifos
    1252
  - Host Mode
    1253
- OTG_FS Interrupts
  1254
- Figure 394. Interrupt Hierarchy
  1255
- OTG_FS Control and Status Registers
  1255
- OTG_FS Programming Model
  1324
  - Host Initialization
    1325
  - Host Programming Model
    1326
    
    Figure 396. Transmit FIFO Write Task
    1327
    
    Figure 397. Receive FIFO Read Task
    1328
    
    Figure 398. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions
    1329
    
    Figure 399. Bulk/Control in Transactions
    1332
    
    Figure 400. Normal Interrupt OUT/IN Transactions
    1334
    
    Figure 401. Normal Isochronous OUT/IN Transactions
    1339
    
    Device Programming Model
    1342
    
    Operational Model
    1344
  - Figure 402. Receive FIFO Packet Read
    1345
  - Figure 403. Processing a SETUP Packet
    1347
  - Figure 404. Bulk out Transaction
    1353
  - Worst Case Response Time
    1360
  - Figure 405. TRDT Max Timing Case
    1362
  - OTG Programming Model
    1362
  - Figure 406. A-Device SRP
    1363
  - Figure 407. B-Device SRP
    1364
  - Figure 408. A-Device HNP
    1365
  - Figure 409. B-Device HNP
    1367
USB On-The-Go High-Speed (OTG_HS)

1369
- General Features
  1370
- Host-Mode Features
  1371
- Figure 410. USB OTG Interface Block Diagram
  1372
- High-Speed OTG PHY
  1372
- OTG Dual-Role Device
  1373
- USB Functional Description in Peripheral Mode
  1374
- Peripheral Endpoints
  1375
- USB Functional Description on Host Mode
  1378
  - Host Channels
    1380
  - Host Scheduler
    1381
  - SOF Trigger
    1382
  - Peripheral Sofs
    1383
- USB_HS Power Modes
  1384
- FIFO RAM Allocation
  1385
- Figure 411. Updating OTG_HS_HFIR Dynamically
  1385
- OTG_HS Interrupts
  1386
- Figure 412. Interrupt Hierarchy
  1387
- OTG_HS Control and Status Registers
  1387
- CSR Memory Map
  1388
- OTG_HS Programming Model
  1473
  - Host Initialization
    1474
  - Device Initialization
    1475
  - Figure 414. Transmit FIFO Write Task
    1478
  - Figure 415. Receive FIFO Read Task
    1479
  - Figure 416. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - DMA
    1480
  - Mode
    1480
  - Figure 417. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - Slave
    1481
  - Mode
    1481
  - Figure 418. Bulk/Control in Transactions - DMA Mode
    1484
  - Figure 419. Bulk/Control in Transactions - Slave Mode
    1485
  - Figure 420. Normal Interrupt OUT/IN Transactions - DMA Mode
    1487
  - Figure 421. Normal Interrupt OUT/IN Transactions - Slave Mode
    1488
  - Figure 422. Normal Isochronous OUT/IN Transactions - DMA Mode
    1493
  - Figure 423. Normal Isochronous OUT/IN Transactions - Slave Mode
    1494
  - Device Programming Model
    1502
  - Operational Model
    1504
  - Figure 424. Receive FIFO Packet Read in Slave Mode
    1505
  - Figure 425. Processing a SETUP Packet
    1507
  - Figure 426. Slave Mode Bulk out Transaction
    1514
  - Worst Case Response Time
    1522
  - Figure 427. TRDT Max Timing Case
    1523
  - Figure 428. A-Device SRP
    1524
  - OTG Programming Model
    1524
  - Figure 429. B-Device SRP
    1525
  - Figure 430. A-Device HNP
    1526
  - Figure 431. B-Device HNP
    1528
Flexible Static Memory Controller (FSMC)

1530
- Figure 432. FSMC Block Diagram
  1531
- Supported Memories and Transactions
  1532
- Table 211. NOR/PSRAM Bank Selection
  1533
- Figure 433. FSMC Memory Banks
  1533
- External Device Address Mapping
  1533
  - NAND/PC Card Address Mapping
    1534
  - Table 212. External Memory Address
    1534
  - Table 213. Memory Mapping and Timing Registers
    1534
  - Table 214. NAND Bank Selections
    1535
- NOR Flash/Psram Controller
  1535
  - External Memory Interface Signals
    1536
  - Table 215. Programmable NOR/PSRAM Access Parameters
    1536
  - Table 216. Nonmultiplexed I/O nor Flash
    1536
  - Table 217. Multiplexed I/O nor Flash
    1537
  - Table 218. Nonmultiplexed I/Os PSRAM/SRAM
    1537
  - Table 219. Multiplexed I/O PSRAM
    1537
  - And Transactions
    1538
  - Supported Memories and Transactions
    1538
  - Table 220. nor Flash/Psram Controller: Example of Supported Memories
    1538
  - General Timing Rules
    1539
  - Figure 434. Mode1 Read Accesses
    1540
  - NOR Flash/Psram Controller Asynchronous Transactions
    1540
  - Figure 435. Mode1 Write Accesses
    1541
  - Table 221. Fsmc_Bcrx Bit Fields
    1541
  - Table 222. Fsmc_Btrx Bit Fields
    1542
  - Figure 436. Modea Read Accesses
    1543
  - Figure 437. Modea Write Accesses
    1543
  - Table 223. Fsmc_Bcrx Bit Fields
    1544
  - Table 224. Fsmc_Btrx Bit Fields
    1544
  - Figure 438. Mode2 and Mode B Read Accesses
    1545
  - Table 225. Fsmc_Bwtrx Bit Fields
    1545
  - Figure 439. Mode2 Write Accesses
    1546
  - Figure 440. Mode B Write Accesses
    1546
  - Table 226. Fsmc_Bcrx Bit Fields
    1547
  - Table 227. Fsmc_Btrx Bit Fields
    1547
  - Figure 441. Mode C Read Accesses
    1548
  - Table 228. Fsmc_Bwtrx Bit Fields
    1548
  - Figure 442. Mode C Write Accesses
    1549
  - Table 229. Fsmc_Bcrx Bit Fields
    1549
  - Table 230. Fsmc_Btrx Bit Fields
    1550
  - Table 231. Fsmc_Bwtrx Bit Fields
    1550
  - Figure 443. Mode D Read Accesses
    1551
  - Figure 444. Mode D Write Accesses
    1551
  - Table 232. Fsmc_Bcrx Bit Fields
    1552
  - Table 233. Fsmc_Btrx Bit Fields
    1552
  - Figure 445. Multiplexed Read Accesses
    1553
  - Table 234. Fsmc_Bwtrx Bit Fields
    1553
  - Figure 446. Multiplexed Write Accesses
    1554
  - Table 235. Fsmc_Bcrx Bit Fields
    1554
  - Table 236. Fsmc_Btrx Bit Fields
    1555
  - Figure 447. Asynchronous Wait During a Read Access
    1556
  - Figure 448. Asynchronous Wait During a Write Access
    1557
  - Synchronous Transactions
    1558
  - Figure 449. Wait Configurations
    1559
  - Figure 450. Synchronous Multiplexed Read Mode - NOR, PSRAM (CRAM)
    1560
  - Table 237. Fsmc_Bcrx Bit Fields
    1560
  - Table 238. Fsmc_Btrx Bit Fields
    1561
  - Figure 451. Synchronous Multiplexed Write Mode - PSRAM (CRAM)
    1562
  - Table 239. Fsmc_Bcrx Bit Fields
    1562
  - Table 240. Fsmc_Btrx Bit Fields
    1563
  - NOR/PSRAM Control Registers
    1564
- NAND Flash/Pc Card Controller
  1571
  - External Memory Interface Signals
    1572
  - Table 241. Programmable NAND/PC Card Access Parameters
    1572
  - Table 242. 8-Bit NAND Flash
    1572
  - Table 243. 16-Bit NAND Flash
    1573
  - Table 244. 16-Bit PC Card
    1573
  - NAND Flash / PC Card Supported Memories and Transactions
    1574
  - Table 245. Supported Memories and Transactions
    1574
  - Figure 452. NAND/PC Card Controller Timing for Common Memory Access
    1575
  - NAND Flash Operations
    1575
  - Figure 453. Access to Non 'CE Don't Care' NAND-Flash
    1576
  - NAND Flash Pre-Wait Functionality
    1576
    
    In NAND Flash Memory
    1577
  - PC Card/Compactflash Operations
    1578
  - Table 246. 16-Bit PC-Card Signals and Access Type
    1579
  - NAND Flash/Pc Card Control Registers
    1580
  - Table 247. ECC Result Relevant Bits
    1586
  - Table 248. FSMC Register Map
    1587
- FMC Main Features
  1589
- Block Diagram
  1590
- Figure 454. FMC Block Diagram
  1591
- AHB Interface
  1591
  - Supported Memories and Transactions
    1592
- External Device Address Mapping
  1593
- NOR Flash/Psram Controller
  1599
  - External Memory Interface Signals
    1600
  - Table 258. Programmable NOR/PSRAM Access Parameters
    1600
  - Table 259. Non-Multiplexed I/O nor Flash Memory
    1601
  - Table 260. 16-Bit Multiplexed I/O nor Flash Memory
    1601
  - Table 261. Non-Multiplexed I/Os PSRAM/SRAM
    1601
  - Supported Memories and Transactions
    1602
  - Table 262. 16-Bit Multiplexed I/O PSRAM
    1602
  - Table 263. nor Flash/Psram: Example of Supported Memories and Transactions
    1603
  - General Timing Rules
    1604
  - Figure 456. Mode1 Read Access Waveforms
    1605
  - Figure 457. Mode1 Write Access Waveforms
    1605
  - Table 264. Fmc_Bcrx Bit Fields
    1606
  - Table 265. Fmc_Btrx Bit Fields
    1606
  - Figure 458. Modea Read Access Waveforms
    1607
  - Figure 459. Modea Write Access Waveforms
    1608
  - Table 266. Fmc_Bcrx Bit Fields
    1608
  - Table 267. Fmc_Btrx Bit Fields
    1609
  - Table 268. Fmc_Bwtrx Bit Fields
    1609
  - Figure 460. Mode2 and Mode B Read Access Waveforms
    1610
  - Figure 461. Mode2 Write Access Waveforms
    1610
  - Figure 462. Modeb Write Access Waveforms
    1611
  - Table 269. Fmc_Bcrx Bit Fields
    1611
  - Table 270. Fmc_Btrx Bit Fields
    1612
  - Table 271. Fmc_Bwtrx Bit Fields
    1612
  - Figure 463. Modec Read Access Waveforms
    1613
  - Figure 464. Modec Write Access Waveforms
    1613
  - Table 272. Fmc_Bcrx Bit Fields
    1614
  - Table 273. Fmc_Btrx Bit Fields
    1614
  - Figure 465. Moded Read Access Waveforms
    1615
  - Table 274. Fmc_Bwtrx Bit Fields
    1615
  - Figure 466. Moded Write Access Waveforms
    1616
  - Table 275. Fmc_Bcrx Bit Fields
    1616
  - Table 276. Fmc_Btrx Bit Fields
    1617
  - Table 277. Fmc_Bwtrx Bit Fields
    1617
  - Figure 467. Muxed Read Access Waveforms
    1618
  - Figure 468. Muxed Write Access Waveforms
    1618
  - Table 278. Fmc_Bcrx Bit Fields
    1619
  - Table 279. Fmc_Btrx Bit Fields
    1619
  - Figure 469. Asynchronous Wait During a Read Access Waveforms
    1620
  - Figure 470. Asynchronous Wait During a Write Access Waveforms
    1621
  - Synchronous Transactions
    1621
  - Figure 471. Wait Configuration Waveforms
    1623
  - Figure 472. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)
    1623
  - Table 280. Fmc_Bcrx Bit Fields
    1624
  - Table 281. Fmc_Btrx Bit Fields
    1624
  - Figure 473. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)
    1625
  - Table 282. Fmc_Bcrx Bit Fields
    1625
  - Table 283. Fmc_Btrx Bit Fields
    1626
  - NOR/PSRAM Controller Registers
    1627
  - NAND Flash/Pc Card Controller
    1634
  - External Memory Interface Signals
    1635
  - Table 284. Programmable NAND Flash/Pc Card Access Parameters
    1635
  - Table 285. 8-Bit NAND Flash
    1635
  - Table 286. 16-Bit NAND Flash
    1636
  - Table 287. 16-Bit PC Card
    1636
  - NAND Flash / PC Card Supported Memories and Transactions
    1637
  - Table 288. Supported Memories and Transactions
    1637
  - Figure 474. NAND Flash/Pc Card Controller Waveforms for Common Memory Access
    1638
  - NAND Flash Operations
    1638
  - Figure 475. Access to Non 'CE Don't Care' NAND-Flash
    1639
  - NAND Flash Prewait Functionality
    1639
  - In NAND Flash Memory
    1640
    
    PC Card/Compactflash Operations
    1641
    
    Table 289. 16-Bit PC-Card Signals and Access Type
    1641
    
    NAND Flash/Pc Card Controller Registers
    1642
  - Table 290. ECC Result Relevant Bits
    1649
  - Table 291. SDRAM Signals
    1650
- SDRAM Controller
  1650
  - SDRAM Controller Functional Description
    1651
  - Figure 476. Burst Write SDRAM Access Waveforms
    1652
  - Figure 477. Burst Read SDRAM Access
    1653
  - Figure 478. Logic Diagram of Read Access with RBURST Bit Set (CAS=2, RPIPE=0)
    1654
  - Figure 479. Read Access Crossing Row Boundary
    1656
  - Figure 480. Write Access Crossing Row Boundary
    1656
  - Low Power Modes
    1657
  - Figure 481. Self-Refresh Mode
    1659
  - Figure 482. Power-Down Mode
    1660
  - SDRAM Controller Registers
    1661
  - Table 292. FMC Register Map
    1667
  - Figure 483. Block Diagram of STM32 MCU and Cortex ® -M4 with FPU-Level
    1670
  - Debug Support
    1670
- Overview
  1670
- SWJ Debug Port (Serial Wire and JTAG)
  1671
- ID Codes and Locking Mechanism
  1677
- SW Debug Port
  1680
  - SW-DP State Machine (Reset, Idle States, ID Code)
    1681
  - Table 298. ACK Response (3 Bits)
    1681
  - Table 299. DATA Transfer (33 Bits)
    1681
  - DP and AP Read/Write Accesses
    1682
  - Table 300. SW-DP Registers
    1682
  - SW-AP Registers
    1683
  - Table 301. Cortex
    1684
  - Table 302. Core Debug Registers
    1685
- Capability of the Debugger Host to Connect under System Reset
  1686
- DWT (Data Watchpoint Trigger)
  1687
- Table 303. Main ITM Registers
  1688
- Table 304. Main ETM Registers
  1689
- ETM (Embedded Trace Macrocell)
  1689
  - Configuration Example
    1690
  - Debug MCU Configuration Register
    1691
  - Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)
    1692
  - Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)
    1694
  - Figure 486. TPIU Block Diagram
    1695
- TPIU (Trace Port Interface Unit)
  1695
  - Table 305. Asynchronous TRACE Pin Assignment
    1696
  - Table 306. Synchronous TRACE Pin Assignment
    1696
  - Table 307. Flexible TRACE Pin Assignment
    1697
  - TPUI Formatter
    1697
  - TPUI Frame Synchronization Packets
    1698
  - Asynchronous Mode
    1699
  - Table 308. Important TPIU Registers
    1699
  - Example of Configuration
    1700
  - Table 309. DBG Register Map and Reset Values
    1700
Device Electronic Signature

1702
- Flash Size
  1703
- Table 310. Document Revision History
  1704

STMicroelectronics Categories

Motherboard Microcontrollers Computer Hardware Controller Control Unit

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STMicroelectronics STM32F415 Manuals

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Table of Contents

Documentation Conventions

Memory and Bus Architecture

Embedded Flash Memory Interface

CRC Calculation Unit

Power Controller (PWR)

Reset and Clock Control for Stm32F42Xxx and Stm32F43Xxx (RCC)

Reset and Clock Control for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC)

General-Purpose I/Os (GPIO)

System Configuration Controller (SYSCFG)

Digital-To-Analog Converter (DAC)

Digital Camera Interface (DCMI)

LCD-TFT Controller (LTDC)

Independent Watchdog (IWDG)

Window Watchdog (WWDG)

Serial Audio Interface (SAI)

Transmitter (USART)

DMA Controller

USB On-The-Go High-Speed (OTG_HS)

Flexible Static Memory Controller (FSMC)

Device Electronic Signature

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