Rcc Apb2 Peripheral Clock Enable Register(Rcc_Apb2Enr) - STMicroelectronics STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
7.3.15

RCC APB2 peripheral clock enable register(RCC_APB2ENR)

Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
SPI1
SYSCF SPI4E
Reser-
G EN N
ved
rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 SPI6EN: SPI6 clock enable
Bit 20 SPI5EN: SPI5 clock enable
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11EN: TIM11 clock enable
Bit 17 TIM10EN: TIM10 clock enable
Bit 16 TIM9EN: TIM9 clock enable
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGEN: System configuration controller clock enable
Bit 13 SPI4EN: SPI4 clock enable
250/1731
28 27 26 25
Reserved
12 11 10 9
SDIO ADC3 ADC2
EN EN EN EN
rw rw rw rw
Set and cleared by software.
0: SPI6 clock disabled
1: SPI6 clock enabled
Set and cleared by software.
0: SPI5 clock disabled
1: SPI5 clock enabled
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
Set and cleared by software.
0: SPI4 clock disabled
1: SPI4 clock enabled
DocID018909 Rev 11
24 23 22 21
SPI6EN SPI5EN
rw
8 7 6 5
USART
ADC1
6
EN
Reserved
EN
rw rw
20 19 18
TIM11 TIM10
EN EN
Res.
rw rw
4 3 2
USART
TIM8
1
EN
Reserved
EN
rw
RM0090
17 16
TIM9
EN
rw rw
1 0
TIM1
EN
rw rw