Figure 411. Updating Otg_Hs_Hfir Dynamically; Fifo Ram Allocation - STMicroelectronics STM32F405 Reference Manual

RM0090
35.10

FIFO RAM allocation

35.10.1 Peripheral mode
Receive FIFO RAM
For Receive FIFO RAM, the application should allocate RAM for SETUP packets: 10
locations must be reserved in the receive FIFO to receive SETUP packets on control
endpoints. These locations are reserved for SETUP packets and are not used by the core to
write any other data.
One location must be allocated for Global OUT NAK. Status information are also written to
the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet
Size / 4) + 1 must be allocated to receive packets. If a high-bandwidth endpoint or multiple
isochronous endpoints are enabled, at least two spaces of (Largest Packet Size / 4) + 1
must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1
spaces are recommended so that when the previous packet is being transferred to AHB, the
USB can receive the subsequent packet.
Along with each endpoints last packet, transfer complete status information are also pushed
to the FIFO. Typically, one location for each OUT endpoint is recommended.
Transmit FIFO RAM
For Transmit FIFO RAM, the minimum RAM space required for each IN Endpoint Transmit
FIFO is the maximum packet size for this IN endpoint.
Note: More space allocated in the transmit IN Endpoint FIFO results in a better performance on
the USB.
35.10.2 Host mode
Receive FIFO RAM
For Receive FIFO RAM allocation, Status information are written to the FIFO along with
each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be
allocated to receive packets. If a high-bandwidth channel or multiple isochronous channels

Figure 411. Updating OTG_HS_HFIR dynamically

DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
1385/1731
1529