Table 127. I; Dma Features - STMicroelectronics STM32F405 Reference Manual

Serial peripheral interface (SPI)
Overrun flag (OVR)
This flag is set when data are received and the previous data have not yet been read from
SPI_DR. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE
bit is set in SPI_CR2.
In this case, the receive buffer contents are not updated with the newly received data from
the transmitter device. A read operation to the SPI_DR register returns the previous
correctly received data. All other subsequently transmitted half-words are lost.
Clearing the OVR bit is done by a read operation on the SPI_DR register followed by a read
access to the SPI_SR register.
Frame error flag (FRE)
This flag can be set by hardware only if the I2S is configured in Slave mode. It is set if the
external master is changing the WS line at a moment when the slave is not expected this
change. If the synchronization is lost, to recover from this state and resynchronize the
external master device with the I2S slave device, follow the steps below:
1. Disable the I2S
2. Re-enable it when the correct level is detected on the WS line (WS line is high in I2S
mode, or low for MSB- or LSB-justified or PCM modes).
Desynchronization between the master and slave device may be due to noisy environment
on the SCK communication clock or on the WS frame synchronization line. An error interrupt
can be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by
software when the status register is read.
2
28.4.9 I S interrupts
Table 127
Transmit buffer empty flag
Receive buffer not empty flag
Overrun error
Underrun error
Frame error flag
28.4.10

DMA features

DMA is working in exactly the same way as for the SPI mode. There is no difference on the
2
I S. Only the CRC feature is not available in I
protection system.
908/1731
2
provides the list of I S interrupts.

Table 127. I

Interrupt event
DocID018909 Rev 11
2
S interrupt requests
Event flag
TXE
RXNE
OVR
UDR
FRE
2
S mode since there is no data transfer
RM0090
Enable Control bit
TXEIE
RXNEIE
ERRIE
ERRIE