Clock Security System (Css); Rtc/Awu Clock - STMicroelectronics STM32F405 Reference Manual

RM0090
6.2.7

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock
failure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an
interrupt is generated to inform the software about the failure (clock security system
interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
®
Cortex -M4 with FPU NMI (non-maskable interrupt) exception vector.
Note: When the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt,
which causes the automatic generation of an NMI. The NMI is executed indefinitely unless
the CSS interrupt pending bit is cleared. As a consequence, the application has to clear the
CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register
(RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that
it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is
detected, then the system clock switches to the HSI oscillator and the HSE oscillator is
disabled.
If the HSE oscillator clock was the clock source of PLL used as the system clock when the
failure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also
disabled when the HSE fails.
6.2.8

RTC/AWU clock

Once the RTCCLK clock source has been selected, the only possible way of modifying the
selection is to reset the power domain.
The RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable
prescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits
in the RCC Backup domain control register (RCC_BDCR)
clock configuration register
resetting the Backup domain.
If the LSE is selected as the RTC clock, the RTC will work normally if the backup or the
system supply disappears. If the LSI is selected as the AWU clock, the AWU state is not
guaranteed if the system supply disappears. If the HSE oscillator divided by a value
between 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup
or the system supply disappears.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a
consequence:
• If LSE is selected as the RTC clock:
–
•
If LSI is selected as the Auto-wakeup unit (AWU) clock:
–
•
If the HSE clock is used as the RTC clock:
–
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
(RCC_CFGR). This selection cannot be modified without
The RTC continues to work even if the V
V supply is maintained.
BAT
The AWU state is not guaranteed if the V
Section 6.2.5: LSI clock on page 156
The RTC state is not guaranteed if the V
voltage regulator is powered off (removing power from the 1.2 V domain).
DocID018909 Rev 11
and the RTCPRE[4:0] bits in
supply is switched off, provided the
DD
supply is powered off. Refer to
DD
for more details on LSI calibration.
supply is powered off or if the internal
DD
RCC
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