Timx Counter (Timx_Cnt) - STMicroelectronics STM32F405 Reference Manual

RM0090
Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
18.4.10

TIMx counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 15:0 CNT[15:0]: Counter value
18.4.11 TIMx prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
18.4.12 TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 15:0
28 27 26 25
CNT[31:16] (depending on timers)
rw rw rw rw
12 11 10 9
rw rw rw rw
12 11 10 9
rw rw rw rw
The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event.
28 27 26 25
ARR[31:16] (depending on timers)
rw rw rw rw
12 11 10 9
rw rw rw rw
ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 18.3.1: Time-base unit on page 583
and behavior.
The counter is blocked while the auto-reload value is null.
DocID018909 Rev 11
General-purpose timers (TIM2 to TIM5)
24 23 22 21
rw rw rw rw
8 7 6 5
CNT[15:0]
rw rw rw rw
8 7 6 5
PSC[15:0]
rw rw rw rw
CK_PSC
24 23 22 21
rw rw rw rw
8 7 6 5
ARR[15:0]
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2
rw rw rw rw
4 3 2
rw rw rw rw
/ (PSC[15:0] + 1).
20 19 18 17
rw rw rw rw
4 3 2
rw rw rw rw
for more details about ARR update
16
rw
1 0
rw
1 0
rw
16
rw
1 0
rw
633/1731
640