Table 67. Configuring The Trigger Polarity; Channel-Wise Programmable Sampling Time - STMicroelectronics STM32F405 Reference Manual

Analog-to-digital converter (ADC)
13.5

Channel-wise programmable sampling time

The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
The total conversion time is calculated as follows:
T
conv
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
T
conv
13.6 Conversion on external trigger and trigger polarity
Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the
EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected
conversion) are different from "0b00", then external events are able to trigger a conversion
with the selected polarity.
and JEXTEN[1:0] values and the trigger polarity.
Trigger detection disabled
Detection on the rising edge
Detection on the falling edge
Detection on both the rising and falling edges
Note: The polarity of the external trigger can be changed on the fly.
The EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible
events can trigger conversion for the regular and injected groups.
Table 68
400/1731
= Sampling time + 12 cycles
= 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz
Table 67

Table 67. Configuring the trigger polarity

Source
gives the possible external trigger for regular conversion.
DocID018909 Rev 11
provides the correspondence between the EXTEN[1:0]
EXTEN[1:0] / JEXTEN[1:0]
00
01
10
11
RM0090