Figure 309. Usart Data Clock Timing Diagram (M=1); Figure 310. Rx Data Setup/Hold Time; Single-Wire Half-Duplex Communication - STMicroelectronics STM32F405 Reference Manual

RM0090
SCLK (capture strobe on SCLK
rising edge in this example)
t
SETUP
Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter
for more details.
30.3.10

Single-wire half-duplex communication

The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
•
LINEN and CLKEN bits in the USART_CR2 register,
•
SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a single-wire half-duplex protocol where the TX and
RX lines are internally connected. The selection between half- and full-duplex
communication is made with a control bit 'HALF DUPLEX SEL' (HDSEL in USART_CR3).
As soon as HDSEL is written to 1:
•
the TX and RX lines are internally connected
•
the RX pin is no longer used
•
the TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as floating input (or output high open-drain) when not driven by the USART.
Universal synchronous asynchronous receiver transmitter (USART)

Figure 309. USART data clock timing diagram (M=1)

Idle or preceding
Start
transmission
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Data on TX
(from master)
Start
Data on RX
(from slave)
Capture Strobe

Figure 310. RX data setup/hold time

Data on RX
(from slave)
= 1/16 bit time
t
HOLD
DocID018909 Rev 11
M=1 (9 data bits)
0 1 2 3 4
LSB
0 1 2 3 4
LSB
valid DATA bit
t
SETUP
Idle or next
Stop
transmission
*
*
*
*
8
5 6 7
MSB Stop
5 6 7 8
MSB
*
* LBCL bit controls last data clock pulse
t
HOLD
989/1731
1010