Table 278. Fmc_Bcrx Bit Fields; Table 279. Fmc_Btrx Bit Fields - STMicroelectronics STM32F405 Reference Manual

RM0090
Bit No.
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
WAIT management in asynchronous accesses
If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.

Table 278. FMC_BCRx bit fields

Bit name
Reserved 0x000
CCLKEN As needed
CBURSTRW 0x0 (no effect in asynchronous mode)
CPSIZE 0x0 (no effect in asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
ASYNCWAIT
0.
EXTMOD 0x0
WAITEN 0x0 (no effect in asynchronous mode)
WREN As needed
WAITCFG Don't care
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN 0x1
MWID As needed
MTYP[1:0] 0x2 (NOR Flash memory)
MUXEN 0x1
MBKEN 0x1

Table 279. FMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles for
DATAST
read accesses and DATAST+1 HCLK cycles for write accesses).
ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET[3:0]
Minimum value for ADDSET is 1.
DocID018909 Rev 11
Flexible memory controller (FMC)
Value to set
Value to set
1619/1731
1669