Flash Access Control Register (Flash_Acr); For Stm32F42Xxx And Stm32F43Xxx - STMicroelectronics STM32F405 Reference Manual

RM0090
3.9.2

Flash access control register (FLASH_ACR)

for STM32F42xxx and STM32F43xxx

The Flash access control register is used to enable/disable the acceleration features and
control the Flash memory access time according to CPU frequency.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
15 14 13 12
DCRST ICRST
Reserved
rw
Bits 31:11 Reserved, must be kept cleared.
Bit 12 DCRST: Data cache reset
This bit can be written only when the D cache is disabled.
Bit 11 ICRST: Instruction cache reset
This bit can be written only when the I cache is disabled.
Bit 10 DCEN: Data cache enable
Bit 9 ICEN: Instruction cache enable
Bit 8 PRFTEN: Prefetch enable
Bits 7:4 Reserved, must be kept cleared.
Bits 3:0 LATENCY[2:0]: Latency
These bits represent the ratio of the CPU clock period to the Flash memory access time.
27 26 25
11 10 9
DCEN ICEN
w rw rw
0: Data cache is not reset
1: Data cache is reset
0: Instruction cache is not reset
1: Instruction cache is reset
0: Data cache is disabled
1: Data cache is enabled
0: Instruction cache is disabled
1: Instruction cache is enabled
0: Prefetch is disabled
1: Prefetch is enabled
0000: Zero wait state
0001: One wait state
0010: Two wait states
...
1110: Fourteen wait states
1111: Fifteen wait states
DocID018909 Rev 11
24 23 22
Reserved
8 7 6
PRFTEN
Reserved
rw
Embedded Flash memory interface
21 20 19 18
5 4 3 2
LATENCY[2:0]
rw rw
17 16
1 0
rw rw
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