Table 235. Fsmc_Bcrx Bit Fields; Figure 446. Multiplexed Write Accesses - STMicroelectronics STM32F405 Reference Manual

Flexible static memory controller (FSMC)
The difference with mode D is the drive of the lower address byte(s) on the databus.
Bit No.
31-21
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1554/1731

Figure 446. Multiplexed write accesses

A[25:16]
NADV
NEx
NOE
NWE
AD[15:0]
ADDSET
HCLK cycles

Table 235. FSMC_BCRx bit fields

Bit name
Reserved
CBURSTRW
CPSIZE
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
MTYP[0:1]
DocID018909 Rev 11
Memory transaction
Lower address
ADDHLD
HCLK cycles
0x000
0x0 (no effect on asynchronous mode)
0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
0.
0x0
0x0 (no effect on asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
0x1
As needed
0x2 (NOR Flash memory)
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
Value to set
RM0090
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