Table 51. Dma Register Map And Reset Values - STMicroelectronics STM32F405 Reference Manual

RM0090
10.5.11 DMA register map
Table 51
Offset Register
DMA_LISR
0x0000
Reset value
DMA_HISR
0x0004
Reset value
DMA_LIFCR
0x0008
Reset value
DMA_HIFCR
0x000C
Reset value
DMA_S0CR
0x0010
Reset value
DMA_S0NDTR
0x0014
Reset value
DMA_S0PAR
0x0018
Reset value 0
DMA_S0M0AR
0x001C
Reset value 0
DMA_S0M1AR
0x0020
Reset value 0
DMA_S0FCR
0x0024
Reset value
DMA_S1CR
0x0028
Reset value
DMA_S1NDTR
0x002C
Reset value
summarizes the DMA registers.

Table 51. DMA register map and reset values

Reserved
0 0 0 0
Reserved
0 0 0 0
Reserved
0 0 0 0
Reserved
0 0 0 0
Reserved
0 0 0 0 0
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
0 0 0 0 0
Reserved
DocID018909 Rev 11
Reserved
0 0 0 0 0 0
Reserved
0 0 0 0 0 0
Reserved
0 0 0 0 0 0
Reserved
0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
M0A[31:0]
0 0 0 0 0 0 0 0 0
M1A[31:0]
0 0 0 0 0 0 0 0 0
Reserved
0 0 0 0 0 0 0 0 0
0 0
DMA controller (DMA)
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
NDT[15:.]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1
0 0 0 0 0 0 0 0 0
NDT[15:.]
0 0 0 0 0 0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
FTH
FS[2:0]
[1:0]
0 0 0 0 1
0 0 0 0 0
0 0 0 0 0
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