Table 250. Nor/Psram External Memory Address; Table 251. Nand/Pc Card Memory Mapping And Timing Registers; Nand Flash Memory/Pc Card Address Mapping - STMicroelectronics STM32F405 Reference Manual

RM0090
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.
Memory width
8-bit
16-bit
32-bit
1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the
address for external memory FMC_A[24:0]. In case of a 32-bit memory width, the FMC will internally use
HADDR[25:2] to generate the external address.
Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].
Wrap support for NOR Flash/PSRAM
Wrap burst mode for synchronous memories is not supported. The memories must be
configured in linear burst mode of undefined length.
37.4.2

NAND Flash memory/PC Card address mapping

In this case, three banks are available, each of them being divided into memory areas as
indicated in
Start address
0x9C00 0000
0x9800 0000
0x9000 0000
0x8800 0000
0x8000 0000
0x7800 0000
0x7000 0000
For NAND Flash memory, the common and attribute memory spaces are subdivided into
three sections (see in
•
Data section (first 64 Kbytes in the common/attribute memory space)
•
Command section (second 64 Kbytes in the common / attribute memory space)
•
Address section (next 128 Kbytes in the common / attribute memory space)

Table 250. NOR/PSRAM External memory address

(1)
Data address issued to the memory
HADDR[25:1] >> 1
HADDR[25:2] >> 2
Table 251.

Table 251. NAND/PC Card memory mapping and timing registers

End address
0x9FFF FFFF
0x9BFF FFFF Bank 4 - PC card
0x93FF FFFF
0x8BFF FFFF
Bank 3 - NAND Flash
0x83FF FFFF
0x7BFF FFFF
Bank 2- NAND Flash
0x73FF FFFF
Table 252
DocID018909 Rev 11
HADDR[25:0]
FMC bank Memory space
Attribute
Common
Attribute
Common
Attribute
Common
below) located in the lower 256 Kbytes:
Flexible memory controller (FMC)
Maximum memory capacity (bits)
64 Mbyte x 8 = 512 Mbit
64 Mbyte/2 x 16 = 512 Mbit
64 Mbyte/4 x 32 = 512 Mbit
Timing register
I/O FMC_PIO4 (0xB0)
FMC_PATT4 (0xAC)
FMC_PMEM4 (0xA8)
FMC_PATT3 (0x8C)
FMC_PMEM3 (0x88)
FMC_PATT2 (0x6C)
FMC_PMEM2 (0x68)
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