Dma2D Background Pfc Control Register (Dma2D_Bgpfccr) - STMicroelectronics STM32F405 Reference Manual

RM0090
11.5.10

DMA2D background PFC control register (DMA2D_BGPFCCR)

Address offset: 0x0024
Reset value: 0x0000 0000
31 30 29 28
ALPHA[7:0]
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15 14 13 12
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Bits 31:24 ALPHA[7: 0]: Alpha value
Bits 23:18 Reserved, must be kept at reset value
Bits 17:16 AM[1: 0]: Alpha mode
Bits 15:8 CS[7: 0]: CLUT size
Bits 7:6 Reserved, must be kept at reset value
27 26 25
rw rw rw
11 10 9
CS[7:0]
rw rw rw
These bits define a fixed alpha channel value which can replace the original alpha value
or be multiplied with the original alpha value according to the alpha mode selected with
bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the
transfer has started, they are read-only.
These bits define which alpha channel value to be used for the background image.
These bits can only be written when data transfers are disabled. Once the transfer has
started, they are read-only.
00: No modification of the foreground image alpha channel value
01: Replace original background image alpha channel value by ALPHA[7: 0]
10: Replace original background image alpha channel value by ALPHA[7:0] multiplied
with original alpha channel value
others: meaningless
These bits define the size of the CLUT used for the BG. Once the CLUT transfer has
started, this field is read-only.
The number of CLUT entries is equal to CS[7:0] + 1.
DocID018909 Rev 11
Chrom-Art Accelerator™ controller (DMA2D)
24 23 22 21
Reserved
rw
8 7 6 5
START
Reserved
rw rc_w1
20 19 18
4 3 2
CCM CM[3:0]
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17 16
AM[1:0]
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1 0
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