Flexible memory controller (FMC)
Bit
number
5-4
3-2
1
0
Bit number
31-30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Bit number
31-30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Note:
The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its
content is don't care.
1612/1731
Table 269. FMC_BCRx bit fields (continued)
Bit name
MWID
As needed
MTYP[1:0]
0x2 (NOR Flash memory)
MUXEN
0x0
MBKEN
0x1
Table 270. FMC_BTRx bit fields
Bit name
Reserved
0x0
ACCMOD
0x1 if extended mode is set
DATLAT
Don't care
CLKDIV
Don't care
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD
Don't care
Duration of the access first phase (ADDSET HCLK cycles) for read
ADDSET[3:0]
accesses. Minimum value for ADDSET is 0.
Table 271. FMC_BWTRx bit fields
Bit name
Reserved
0x0
ACCMOD
0x1 if extended mode is set
DATLAT
Don't care
CLKDIV
Don't care
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
write accesses.
ADDHLD
Don't care
Duration of the access first phase (ADDSET HCLK cycles) for write
ADDSET[3:0]
accesses. Minimum value for ADDSET is 0.
DocID018909 Rev 11
Value to set
Value to set
Value to set
RM0090
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