Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr) - STMicroelectronics STM32F405 Reference Manual

RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
7.3.20 RCC APB2 peripheral clock enabled in low power mode
register (RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0407 5F33
Access: no wait state, word, half-word and byte access.
31 30 29 28
15 14 13 12
SYSC
SPI1
FG
Reser- Reser-
LPEN
LPEN
ved ved
rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode
Bit 11 SDIOLPEN: SDIO clock enable during Sleep mode
27 26 25
Reserved
11 10 9
SDIO ADC3 ADC2
LPEN LPEN LPEN
rw rw rw
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
Set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode
Set and cleared by software.
0: SPI1 clock disabled during Sleep mode
1: SPI1 clock enabled during Sleep mode
Set and cleared by software.
0: SDIO module clock disabled during Sleep mode
1: SDIO module clock enabled during Sleep mode
DocID018909 Rev 11
24 23 22 21
8 7 6 5
USART
ADC1
6
LPEN
Reserved
LPEN
rw rw
20 19 18
TIM11 TIM10
LPEN LPEN
rw
4 3 2
USART
TIM8
1
LPEN
Reserved
LPEN
rw
17 16
TIM9
LPEN
rw rw
1 0
TIM1
LPEN
rw rw
259/1731
268