Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - STMicroelectronics STM32F405 Reference Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
6.3.9

RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
Reserved
15 14 13
SPI1
SYSCF SPI4
Reser-
G RST RST
RST
ved
rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 LTDCRST: LTDC reset
Bits 27:23 Reserved, must be kept at reset value.
Bit 22 SAI1RST: SAI1 reset
Bit 21 SPI6RST: SPI6 reset
Bit 20 SPI5RST: SPI5 reset
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
Bit 17 TIM10RST: TIM10 reset
Bit 16 TIM9RST: TIM9 reset
178/1731
28 27 26 25
LTD
CRST
rw
12 11 10 9
SDIO
RST
Reserved
rw rw
This bit is set and reset by software.
0: does not reset LCD-TFT
1: resets LCD-TFT
This bit is set and reset by software.
0: does not reset SAI1
1: resets SAI1
This bit is set and cleared by software.
0: does not reset SPI6
1: resets SPI6
This bit is set and cleared by software.
0: does not reset SPI5
1: resets SPI5
This bit is set and cleared by software.
0: does not reset TIM11
1: resets TIM14
This bit is set and cleared by software.
0: does not reset TIM10
1: resets TIM10
This bit is set and cleared by software.
0: does not reset TIM9
1: resets TIM9
DocID018909 Rev 11
24 23 22
SAI1
RST
Reserved
rw
8 7 6
USART
ADC
RST
Reserved
rw
21 20 19 18
TIM11
SPI6 SPI5
RST RST
RST
Res.
rw rw rw
5 4 3 2
USART
6 1
Reserved
RST RST
rw rw
RM0090
17 16
TIM10 TIM9
RST RST
rw rw
1 0
TIM8 TIM1
RST RST
rw rw