Peripheral Sofs - STMicroelectronics STM32F405 Reference Manual

RM0090
SOF trigger output to TIM2 ITR1 connection
35.7.2

Peripheral SOFs

In peripheral mode, the start of frame interrupt is generated each time an SOF token is
received on the USB (SOF bit in OTG_HS_GINTSTS). The corresponding frame number
can be read from the device status register (FNSOF bit in OTG_HS_DSTS). An SOF pulse
signal with a width of 12 system clock cycles is also generated and can be made available
externally on the SOF pin by using the SOF output enable bit in the global control and
configuration register (SOFOUTEN bit in OTG_HS_GCCFG). The SOF pulse signal is also
internally connected to the TIM2 input trigger, so that the input capture feature, the output
compare feature and the timer can be triggered by the SOF pulse (see
connection is enabled through ITR1_RMP bits of TIM2_OR register.
The end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when
80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame
interval field in the device configuration register (PFIVL bit in OTG_HS_DCFG).
This feature can be used to determine if all of the isochronous traffic for that frame is
complete.
OTG_HS_Core
ITR1
SOF
pulse
TIM2
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
SOF output pulse
VBUS
DP
DM
ID
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Figure ). The TIM2
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