Rcc Dedicated Clock Configuration Register (Rcc_Dckcfgr) - STMicroelectronics STM32F405 Reference Manual

RM0090
Bits 23:15 Reserved, must be kept at reset value.
Bits 14:6 PLLSAIN: PLLSAI division factor for VCO
These bits are set and cleared by software to control the multiplication factor of the VCO.
These bits can be written only when PLLSAI is disabled. Only half-word and word accesses
are allowed to write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output frequency
VCO output frequency = VCO input frequency × PLLISAIN with 50 ≤ PLLISAIN ≤ 432
000000000: PLLISAIN = 0, wrong configuration
000000001: PLLISAIN = 1, wrong configuration
...
000110010: PLLISAIN = 50
...
001100011: PLLISAIN = 99
001100100: PLLISAIN = 100
001100101: PLLISAIN = 101
001100110: PLLISAIN = 102
...
110110000: PLLISAIN = 432
110110001: PLLISAIN = 433, wrong configuration
...
111111111: PLLISAIN = 511, wrong configuration
Note: Multiplication factors ranging from 50 and 99 are possible for VCO input frequency
Bits 5:0 Reserved, must be kept at reset value
6.3.25

RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)

Address offset: 0x8C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
The RCC_DCKCFGR register allows to configure the timer clock prescalers and the PLLSAI
and PLLI2S output clock dividers for SAI1 and LTDC peripherals according to the following
formula:
f
(PLLSAIDIVQ clock output)
f
(PLLSAIDIVR clock output)
f(
PLLI2SDIVQ clock output)
31 30 29 28
Reserved
15 14 13 12
Reserved
rw
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
is between 100 and 432 MHz.
higher than 1 MHz. However care must be taken that the minimum VCO output
frequency respects the value specified above.
= f
(PLLSAI_Q)
= f
(PLLSAI_R)
= f
(PLLI2S_Q)
27 26 25
TIMPRE
11 10 9
PLLSAIDIVQ
rw rw rw
DocID018909 Rev 11
/ PLLSAIDIVQ
/ PLLSAIDIVR
/ PLLI2SDIVQ
24 23 22 21
SAI1BSRC SAI1ASRC
rw rw rw rw
8 7 6 5
Reserved
rw
20 19 18 17
PLLSAIDIVR
Reserved
rw rw
4 3 2 1
PLLS2DIVQ
rw rw rw rw
16
rw
0
rw
207/1731
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