Table 210. Otg_Hs Register Map And Reset Values - STMicroelectronics STM32F405 Reference Manual

USB on-the-go high-speed (OTG_HS)
35.12.5 OTG_HS power and clock gating control register
(OTG_HS_PCGCCTL)
Address offset: 0xE00
Reset value: 0x0000 0000
This register is available in host and peripheral modes.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit 31:5 Reserved, must be kept at reset value.
Bit 4 PHYSUSP: PHY suspended
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 GATEHCLK: Gate HCLK
Bit 0 STPPCLK: Stop PHY clock
35.12.6 OTG_HS register map
The table below gives the USB OTG register map and reset values.
Offset Register
OTG_HS_GO
TGCTL
0x000
Reset value
OTG_HS_GO
TGINT
0x004
Reset value
OTG_HS_GA
HBCFG
0x008
Reset value
1458/1731
Reserved
Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended
after the application has set the STPPCLK bit (bit 0).
The application sets this bit to gate HCLK to modules other than the AHB Slave and Master
and wakeup logic when the USB is suspended or the session is not valid. The application
clears this bit when the USB is resumed or a new session starts.
The application sets this bit to stop the PHY clock when the USB is suspended, the session
is not valid, or the device is disconnected. The application clears this bit when the USB is
resumed or a new session starts.

Table 210. OTG_HS register map and reset values

Reserved
Reserved
DocID018909 Rev 11
Reserved
0 0 0 1
0 0 0
Reserved
9 8 7 6 5 4 3
rw
Reserved
0 0 0 0
Reserved
0 0
Reserved
0 0
RM0090
2 1 0
rw rw
0 0
Res.
0
0