Figure 434. Mode1 Read Accesses; Nor Flash/Psram Controller Asynchronous Transactions - STMicroelectronics STM32F405 Reference Manual

Flexible static memory controller (FSMC)
36.5.4

NOR Flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR Flash memory, PSRAM, SRAM)
• Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
•
The FSMC always samples the data before de-asserting the NOE signals. This
guarantees that the memory data-hold timing constraint is met (chip enable high to
data transition, usually 0 ns min.)
•
If the extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up
to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and
D modes for read and write operations. For example, read operation can be performed
in mode A and write in mode B.
•
If the extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register),
the FSMC can operate in Mode1 or Mode2 as follows:
–
–
Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by
the required configuration of FSMC _BCRx, and FSMC_BTRx/FSMC_BWTRx registers.
A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]
1. NBL[1:0] are driven low during read access.
1540/1731
Mode 1 is the default mode when SRAM/PSRAM memory type is selected
(MTYP[0:1] = 0x0 or 0x01 in the FSMC_BCRx register)
Mode 2 is the default mode when NOR memory type is selected (MTYP[0:1] =
0x10 in the FSMC_BCRx register).

Figure 434. Mode1 read accesses

High
ADDSET
HCLK cycles
DocID018909 Rev 11
Memory transaction
data driven
by memory
DATAST
HCLK cycles
RM0090
ai15557