Figure 118. Edge-Aligned Pwm Waveforms (Arr=8) - STMicroelectronics STM32F405 Reference Manual

RM0090
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
•
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
Section : Upcounting mode on page
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at '1'. If the compare value is 0 then OCxRef is held at '0'.
Figure 118
TIMx_ARR=8.
•
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to
Downcounting mode on page 519
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at '1'. 0% PWM
is not possible in this mode.
shows some edge-aligned PWM waveforms in an example where

Figure 118. Edge-aligned PWM waveforms (ARR=8)

Counter register
OCXREF
CCRx=4
CCxIF
OCXREF
CCRx=8
CCxIF
OCXREF
CCRx>8
CCxIF
OCXREF
CCRx=0
CCxIF
DocID018909 Rev 11
Advanced-control timers (TIM1&TIM8)
516.
0 1 2 3 4 5
'1'
'0'
6 7 8 0 1
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