Table 282. Fmc_Bcrx Bit Fields; Figure 473. Synchronous Multiplexed Write Mode Waveforms - Psram (Cram) - STMicroelectronics STM32F405 Reference Manual

RM0090

Figure 473. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed
to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Bit No.
31-20
20
19
18-16
15
14
13
12

Table 282. FMC_BCRx bit fields

Bit name
Reserved 0x000
CCLKEN As needed
CBURSTRW 0x1
CPSIZE As needed (0x1 for CRAM 1.5)
ASYNCWAIT 0x0
EXTMOD 0x0
to be set to 1 if the memory supports this feature, to be kept at 0
WAITEN
otherwise.
WREN 0x1
DocID018909 Rev 11
Flexible memory controller (FMC)
Value to set
1625/1731
1669